/** @file
  Intel ACPI Reference Code for Pch Rootport Endpoint Wrapper

@copyright
  INTEL CONFIDENTIAL
  Copyright 2013 - 2020 Intel Corporation.

  The source code contained or described herein and all documents related to the
  source code ("Material") are owned by Intel Corporation or its suppliers or
  licensors. Title to the Material remains with Intel Corporation or its suppliers
  and licensors. The Material may contain trade secrets and proprietary and
  confidential information of Intel Corporation and its suppliers and licensors,
  and is protected by worldwide copyright and trade secret laws and treaty
  provisions. No part of the Material may be used, copied, reproduced, modified,
  published, uploaded, posted, transmitted, distributed, or disclosed in any way
  without Intel's prior express written permission.

  No license under any patent, copyright, trade secret or other intellectual
  property right is granted to or conferred upon you by disclosure or delivery
  of the Materials, either expressly, by implication, inducement, estoppel or
  otherwise. Any license under such intellectual property rights must be
  express and approved by Intel in writing.

  Unless otherwise agreed by Intel in writing, you may not remove or alter
  this notice or any other notice embedded in Materials by Intel or
  Intel's suppliers or licensors in any way.

  This file contains a 'Sample Driver' and is licensed as such under the terms
  of your license agreement with Intel or your vendor. This file may be modified
  by the user, subject to the additional terms of the license agreement.

@par Specification Reference:
**/

//
// PCIe endpoint PCI config space to MMIO address
//
// Arg0 - _ADR of the target root port controller.
// Arg1 - _ADR of the target endpoint device.
//
Method (GMIO, 2, Serialized) { // Get Memory Mapped I/O address
  // Bus number will be grabbed from the root port. (under the scope where this method exists)
  // Root port PCI config space definition
  OperationRegion (PXCS, SystemMemory, \_SB.PC00.PC2M(Arg0), 0x20) // PCI eXpress Configuration Space
  Field (PXCS, AnyAcc, NoLock, Preserve) {
    Offset(0x18), // Bus Number register
    PBUS, 8,      // Primary Bus Number
    SBUS, 8,      // Subordinate Bus Number
  }
  Store (\_SB.PC00.GPCB(), Local0) // MMIO Base address
  Add (Local0, ShiftRight(And(Arg1,0x001F0000), 1), Local0)  // Device no
  Add (Local0, ShiftLeft(And(Arg1, 0x00000007), 12), Local0) // Function no
  Add (Local0, ShiftLeft(SBUS, 20), Local0)                  // Bus no

  Return (Local0)
}

Scope (\_SB.PC00.RP01.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP01
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP02.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP02
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP03.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP03
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP04.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP04
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP05.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP05
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP06.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP06
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP07.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP07
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP08.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP08
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP09.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP09
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP10.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP10
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP11.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP11
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP12.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP12
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP13.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP13
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP14.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP14
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP15.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP15
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP16.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP16
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP17.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP17
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP18.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP18
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP19.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP19
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP20.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP20
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP21.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP21
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP22.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP22
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP23.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP23
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP24.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP24
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP25.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP25
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP26.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP26
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP27.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP27
  Include("DiscreteConnectivity.asl")
}

Scope (\_SB.PC00.RP28.PXSX)
{
  #undef PCIE_ROOT_PORT
  #define PCIE_ROOT_PORT \_SB.PC00.RP28
  Include("DiscreteConnectivity.asl")
}