## @file
#  AlderLake S RVP GPIO definition table for Pre-Memory Initialization
#
# @copyright
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#  This file contains a 'Sample Driver' and is licensed as such under the terms
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#
# @par Specification
##

###
### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
###
###

# mGpioTablePreMemAdlSDdr4UDimm2DCrb
[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr4UDimm2DCrb]
gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
  { GPIO_VER4_S_GPP_E2,   {GpioPadModeGpio,   GpioHostOwnAcpi,   GpioDirOut,     GpioOutHigh,     GpioIntDefault,          GpioPlatformReset,   GpioTermNone }}, // PEG_1 RTD3 Reset
  { GPIO_VER4_S_GPP_E3,   {GpioPadModeGpio,   GpioHostOwnAcpi,   GpioDirOut,     GpioOutHigh,     GpioIntDefault,          GpioPlatformReset,   GpioTermNone }}, // PEG_2 RTD3 Reset Sinai DR0 (Rework)
  { GPIO_VER4_S_GPP_F11,  {GpioPadModeGpio,   GpioHostOwnAcpi,   GpioDirOut,     GpioOutHigh,     GpioIntDefault,          GpioPlatformReset,   GpioTermNone }}, // PCIe SLOT_1 RTD3 Reset MIPI60 (Rework)
  { GPIO_VER4_S_GPP_F12,  {GpioPadModeGpio,   GpioHostOwnAcpi,   GpioDirOut,     GpioOutHigh,     GpioIntDefault,          GpioHostDeepReset,   GpioTermNone }}, // PCIe SLOT_2 RTD3 Reset MIPI60 (Rework)
  { GPIO_VER4_S_GPP_F13,  {GpioPadModeGpio,   GpioHostOwnAcpi,   GpioDirOut,     GpioOutHigh,     GpioIntDefault,          GpioPlatformReset,   GpioTermNone }}, // PCIe SLOT_3 RTD3 Reset MIPI60 (Rework)
  { 0x0 }  // terminator
})}

# mGpioTablePreMemAdlSDdr5UDimm1DCrb
[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5UDimm1DCrb]
gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
  {GPIO_VER4_S_GPP_E2,   {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//CPU PEG Slot1 Reset
  {GPIO_VER4_S_GPP_F11,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//PCIE SLOT 1 - X4 CONNECTOR Reset
  {GPIO_VER4_S_GPP_F12,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioHostDeepReset,  GpioTermNone}},//PCIE SLOT 2 - X4 CONNECTOR Reset
  {GPIO_VER4_S_GPP_F13,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//PCIE SLOT 3 - X2 CONNECTOR Reset
  {0x0}  // terminator
})}

# mGpioTablePreMemAdlSDdr5UDimm1DAep
[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5UDimm1DAep]
gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
  {GPIO_VER4_S_GPP_E2,   {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,     GpioOutHigh,    GpioIntDefault,           GpioPlatformReset, GpioTermNone }},// PEG SLOT RST_N
  {GPIO_VER4_S_GPP_K4,   {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,     GpioOutHigh,    GpioIntDefault,           GpioResetDefault,  GpioTermNone }},// Maple Ridge 1 (Back Panel) TBT_BP_RST_N
  {GPIO_VER4_S_GPP_K3,   {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,     GpioOutHigh,    GpioIntDefault,           GpioResetDefault,  GpioTermNone }},// Maple Ridge 2 (Front Panel) TBT_FP_RST_N
  {0x0}  // terminator
})}

# mGpioTablePreMemmAdlSSbgaDdr5SODimmErb
[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr5SODimmErb]
gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
  {GPIO_VER4_S_GPP_E2,   {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//CPU PEG Slot Reset
  {GPIO_VER4_S_GPP_E17,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//PCIE SLOT x4 Reset
  {GPIO_VER4_S_GPP_F18,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//M.2 CPU SSD reset
  {GPIO_VER4_S_GPP_C10,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//PCH SSD Reset
  {0x0}  // terminator
})}

# mGpioTablePreMemmAdlSSbgaDdr4SODimmCrb
[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr4SODimmCrb]
gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
  {GPIO_VER4_S_GPP_E2,   {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}}, // CPU PEG Slot Reset
  {GPIO_VER4_S_GPP_F22,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}}, // PCIESLOT_1_RST_N
  {GPIO_VER4_S_GPP_C10,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}}, // PCH SSD Reset
  {GPIO_VER4_S_GPP_F11,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}}, // CPU SSD reset
  {0x0}  // terminator
})}

# mGpioTablePreMemAdlSAdpSSbgaDdr5SODimmAep
[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr5SODimmAep]
gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
  {GPIO_VER4_S_GPP_E2,   {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//CPU PEG Slot Reset
  {GPIO_VER4_S_GPP_F18,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//PCH SSD1 reset
  {GPIO_VER4_S_GPP_C10,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,     GpioOutHigh,      GpioIntDefault,          GpioPlatformReset,  GpioTermNone}},//PCH SSD2 Reset
  {0x0}  // terminator
})}