//
// Automatically generated by GenNvs ver 2.4.6
// Please DO NOT modify !!!
//

/**@file

@copyright
  INTEL CONFIDENTIAL
  Copyright 2017 - 2020 Intel Corporation.

  The source code contained or described herein and all documents related to the
  source code ("Material") are owned by Intel Corporation or its suppliers or
  licensors. Title to the Material remains with Intel Corporation or its suppliers
  and licensors. The Material may contain trade secrets and proprietary and
  confidential information of Intel Corporation and its suppliers and licensors,
  and is protected by worldwide copyright and trade secret laws and treaty
  provisions. No part of the Material may be used, copied, reproduced, modified,
  published, uploaded, posted, transmitted, distributed, or disclosed in any way
  without Intel's prior express written permission.

  No license under any patent, copyright, trade secret or other intellectual
  property right is granted to or conferred upon you by disclosure or delivery
  of the Materials, either expressly, by implication, inducement, estoppel or
  otherwise. Any license under such intellectual property rights must be
  express and approved by Intel in writing.

  Unless otherwise agreed by Intel in writing, you may not remove or alter
  this notice or any other notice embedded in Materials by Intel or
  Intel's suppliers or licensors in any way.

  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
  the terms of your license agreement with Intel or your vendor. This file may
  be modified by the user, subject to additional terms of the license agreement.

@par Specification Reference:
**/

  //
  // Define DTBT NVS Area operation region.
  //
#ifndef _D_TBT_NVS_AREA_DEF_H_
#define _D_TBT_NVS_AREA_DEF_H_

#pragma pack (push,1)
typedef struct {
  UINT8    TbtWin10Support;                         ///< Offset 0       TbtWin10Support
  UINT8    ThunderboltHotNotify;                    ///< Offset 1       Notify on Hot Plug for TBT devices
  UINT8    TbtAcpiRemovalSupport;                   ///< Offset 2       TbtAcpiRemovalSupport
  UINT8    TbtWakeupSupport;                        ///< Offset 3       Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
  UINT8    DiscreteTbtSupport;                      ///< Offset 4       Thunderbolt (TM) support
  UINT8    TbtGpioFilter;                           ///< Offset 5       Gpio filter to detect USB Hotplug event
  UINT32   TbtCioPlugEventGpioNo0;                  ///< Offset 6       TbtCioPlugEventGpioNo
  UINT32   TbtPcieRstGpioNo0;                       ///< Offset 10      TbtPcieRstGpioNo
  UINT8    TbtPcieRstGpioLevel0;                    ///< Offset 14      TbtPcieRstGpioLevel
  UINT8    CurrentDiscreteTbtRootPort;              ///< Offset 15      Current Port that has plug event
  UINT8    RootportSelected0;                       ///< Offset 16      Root port Selected by the User
  UINT8    RootportSelected0Type;                   ///< Offset 17      Root port Type
  UINT8    RootportSelected1;                       ///< Offset 18      Root port Selected by the User
  UINT8    RootportSelected1Type;                   ///< Offset 19      Root port Type
  UINT8    RootportEnabled0;                        ///< Offset 20      Root port Enabled by the User
  UINT8    RootportEnabled1;                        ///< Offset 21      Root port Enabled by the User
  UINT32   TbtCioPlugEventGpioNo1;                  ///< Offset 22      TbtCioPlugEventGpioNo
  UINT32   TbtPcieRstGpioNo1;                       ///< Offset 26      TbtPcieRstGpioNo
  UINT8    TbtPcieRstGpioLevel1;                    ///< Offset 30      TbtPcieRstGpioLevel
  UINT8    TBtCommonGpioSupport;                    ///< Offset 31      Set if Single GPIO is used for Multi/Different Controller Hot plug support
  UINT8    CurrentDiscreteTbtRootPortType;          ///< Offset 32      Root Port type for which SCI Triggered
  UINT8    DTbtControllerEn0;                       ///< Offset 33      DTbtController0 is enabled or not.   @deprecated since revision 2
  UINT8    DTbtControllerEn1;                       ///< Offset 34      DTbtController1 is enabled or not.   @deprecated since revision 2
  UINT8    DTbtRtd3;                                ///< Offset 35      DTBT Rtd3.
  UINT16   DTbtRtd3OffDelay;                        ///< Offset 36      DTBT RTD3 Off delay in ms.
  UINT8    DTbtRtd3ClkReq;                          ///< Offset 38      Enable DTBT RTD3 CLKREQ mask.
  UINT16   DTbtRtd3ClkReqDelay;                     ///< Offset 39      DTBT RTD3 CLKREQ mask delay.
  UINT8    DTbtGo2SxCommand;                        ///< Offset 41      DTBT Go2Sx command.
  //
  // Revision Field:
  //
  UINT8    DTbtRevision;                            ///< Offset 42      Revison of DTbtNvsArea
  UINT8    TbtBootDeviceConnected;                  ///< Offset 43      Tbt Boot Device Connected.
  UINT8    DTbtControllerPresentNo;                 ///< Offset 44      Total DTBT controllers present.
  UINT8    DTbtRtd3OffDelayOptEn;                   ///< Offset 45      DTBT RTD3 Off delay Optimization Enable.
} DTBT_NVS_AREA;

#pragma pack(pop)
#endif