// // Automatically generated by GenNvs ver 2.4.6 // Please DO NOT modify !!! // /**@file @copyright INTEL CONFIDENTIAL Copyright 2013 - 2021 Intel Corporation. The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission. No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing. Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way. This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement. @par Specification Reference: **/ // // Define PCH NVS Area operatino region. // OperationRegion(PNVA,SystemMemory,PNVB,PNVL) Field(PNVA,AnyAcc,Lock,Preserve) { Offset(0), PCHS, 16, // Offset(0), PCH Series Offset(2), PCHG, 16, // Offset(2), PCH Generation Offset(4), PSTP, 16, // Offset(4), PCH Stepping Offset(6), RPA1, 32, // Offset(6), Root Port address 1 Offset(10), RPA2, 32, // Offset(10), Root Port address 2 Offset(14), RPA3, 32, // Offset(14), Root Port address 3 Offset(18), RPA4, 32, // Offset(18), Root Port address 4 Offset(22), RPA5, 32, // Offset(22), Root Port address 5 Offset(26), RPA6, 32, // Offset(26), Root Port address 6 Offset(30), RPA7, 32, // Offset(30), Root Port address 7 Offset(34), RPA8, 32, // Offset(34), Root Port address 8 Offset(38), RPA9, 32, // Offset(38), Root Port address 9 Offset(42), RPAA, 32, // Offset(42), Root Port address 10 Offset(46), RPAB, 32, // Offset(46), Root Port address 11 Offset(50), RPAC, 32, // Offset(50), Root Port address 12 Offset(54), RPAD, 32, // Offset(54), Root Port address 13 Offset(58), RPAE, 32, // Offset(58), Root Port address 14 Offset(62), RPAF, 32, // Offset(62), Root Port address 15 Offset(66), RPAG, 32, // Offset(66), Root Port address 16 Offset(70), RPAH, 32, // Offset(70), Root Port address 17 Offset(74), RPAI, 32, // Offset(74), Root Port address 18 Offset(78), RPAJ, 32, // Offset(78), Root Port address 19 Offset(82), RPAK, 32, // Offset(82), Root Port address 20 Offset(86), RPAL, 32, // Offset(86), Root Port address 21 Offset(90), RPAM, 32, // Offset(90), Root Port address 22 Offset(94), RPAN, 32, // Offset(94), Root Port address 23 Offset(98), RPAO, 32, // Offset(98), Root Port address 24 Offset(102), RPAP, 32, // Offset(102), Root Port address 25 Offset(106), RPAQ, 32, // Offset(106), Root Port address 26 Offset(110), RPAR, 32, // Offset(110), Root Port address 27 Offset(114), RPAS, 32, // Offset(114), Root Port address 28 Offset(118), NHLA, 64, // Offset(118), HD-Audio NHLT ACPI address Offset(126), NHLL, 32, // Offset(126), HD-Audio NHLT ACPI length Offset(130), ADFM, 32, // Offset(130), HD-Audio DSP Feature Mask Offset(134), SWQ0, 8, // Offset(134), HD-Audio SoundWire Link #1 quirk mask Offset(135), SWQ1, 8, // Offset(135), HD-Audio SoundWire Link #2 quirk mask Offset(136), SWQ2, 8, // Offset(136), HD-Audio SoundWire Link #3 quirk mask Offset(137), SWQ3, 8, // Offset(137), HD-Audio SoundWire Link #4 quirk mask Offset(138), ACS0, 8, // Offset(138), HD-Audio SoundWire Link #1 Autonomous Clock Stop Offset(139), ACS1, 8, // Offset(139), HD-Audio SoundWire Link #2 Autonomous Clock Stop Offset(140), ACS2, 8, // Offset(140), HD-Audio SoundWire Link #3 Autonomous Clock Stop Offset(141), ACS3, 8, // Offset(141), HD-Audio SoundWire Link #4 Autonomous Clock Stop Offset(142), DAI0, 8, // Offset(142), HD-Audio SoundWire Link #1 Data On Active Interval Select Offset(143), DAI1, 8, // Offset(143), HD-Audio SoundWire Link #2 Data On Active Interval Select Offset(144), DAI2, 8, // Offset(144), HD-Audio SoundWire Link #3 Data On Active Interval Select Offset(145), DAI3, 8, // Offset(145), HD-Audio SoundWire Link #4 Data On Active Interval Select Offset(146), DOD0, 8, // Offset(146), HD-Audio SoundWire Link #1 Data On Delay Select Offset(147), DOD1, 8, // Offset(147), HD-Audio SoundWire Link #2 Data On Delay Select Offset(148), DOD2, 8, // Offset(148), HD-Audio SoundWire Link #3 Data On Delay Select Offset(149), DOD3, 8, // Offset(149), HD-Audio SoundWire Link #4 Data On Delay Select Offset(150), SWMC, 8, // Offset(150), HD-Audio SoundWire Host Count Offset(151), XTAL, 32, // Offset(151), XTAL frequency: 0: 24MHz; 1: 38.4MHz; 2: Unsupported Offset(155), AFDF, 8, // Offset(155), Audio FPGA Number of Device and Function. 0: Audio FPGA not detected Offset(156), SBRG, 32, // Offset(156), SBREG_BAR Offset(160), GEI0, 8, // Offset(160), GPIO GroupIndex mapped to GPE_DW0 Offset(161), GEI1, 8, // Offset(161), GPIO GroupIndex mapped to GPE_DW1 Offset(162), GEI2, 8, // Offset(162), GPIO GroupIndex mapped to GPE_DW2 Offset(163), GED0, 8, // Offset(163), GPIO DW part of group mapped to GPE_DW0 Offset(164), GED1, 8, // Offset(164), GPIO DW part of group mapped to GPE_DW1 Offset(165), GED2, 8, // Offset(165), GPIO DW part of group mapped to GPE_DW2 Offset(166), PML1, 16, // Offset(166), PCIE LTR max snoop Latency 1 Offset(168), PML2, 16, // Offset(168), PCIE LTR max snoop Latency 2 Offset(170), PML3, 16, // Offset(170), PCIE LTR max snoop Latency 3 Offset(172), PML4, 16, // Offset(172), PCIE LTR max snoop Latency 4 Offset(174), PML5, 16, // Offset(174), PCIE LTR max snoop Latency 5 Offset(176), PML6, 16, // Offset(176), PCIE LTR max snoop Latency 6 Offset(178), PML7, 16, // Offset(178), PCIE LTR max snoop Latency 7 Offset(180), PML8, 16, // Offset(180), PCIE LTR max snoop Latency 8 Offset(182), PML9, 16, // Offset(182), PCIE LTR max snoop Latency 9 Offset(184), PMLA, 16, // Offset(184), PCIE LTR max snoop Latency 10 Offset(186), PMLB, 16, // Offset(186), PCIE LTR max snoop Latency 11 Offset(188), PMLC, 16, // Offset(188), PCIE LTR max snoop Latency 12 Offset(190), PMLD, 16, // Offset(190), PCIE LTR max snoop Latency 13 Offset(192), PMLE, 16, // Offset(192), PCIE LTR max snoop Latency 14 Offset(194), PMLF, 16, // Offset(194), PCIE LTR max snoop Latency 15 Offset(196), PMLG, 16, // Offset(196), PCIE LTR max snoop Latency 16 Offset(198), PMLH, 16, // Offset(198), PCIE LTR max snoop Latency 17 Offset(200), PMLI, 16, // Offset(200), PCIE LTR max snoop Latency 18 Offset(202), PMLJ, 16, // Offset(202), PCIE LTR max snoop Latency 19 Offset(204), PMLK, 16, // Offset(204), PCIE LTR max snoop Latency 20 Offset(206), PMLL, 16, // Offset(206), PCIE LTR max snoop Latency 21 Offset(208), PMLM, 16, // Offset(208), PCIE LTR max snoop Latency 22 Offset(210), PMLN, 16, // Offset(210), PCIE LTR max snoop Latency 23 Offset(212), PMLO, 16, // Offset(212), PCIE LTR max snoop Latency 24 Offset(214), PMLP, 16, // Offset(214), PCIE LTR max snoop Latency 25 Offset(216), PMLQ, 16, // Offset(216), PCIE LTR max snoop Latency 26 Offset(218), PMLR, 16, // Offset(218), PCIE LTR max snoop Latency 27 Offset(220), PMLS, 16, // Offset(220), PCIE LTR max snoop Latency 28 Offset(222), PNL1, 16, // Offset(222), PCIE LTR max no snoop Latency 1 Offset(224), PNL2, 16, // Offset(224), PCIE LTR max no snoop Latency 2 Offset(226), PNL3, 16, // Offset(226), PCIE LTR max no snoop Latency 3 Offset(228), PNL4, 16, // Offset(228), PCIE LTR max no snoop Latency 4 Offset(230), PNL5, 16, // Offset(230), PCIE LTR max no snoop Latency 5 Offset(232), PNL6, 16, // Offset(232), PCIE LTR max no snoop Latency 6 Offset(234), PNL7, 16, // Offset(234), PCIE LTR max no snoop Latency 7 Offset(236), PNL8, 16, // Offset(236), PCIE LTR max no snoop Latency 8 Offset(238), PNL9, 16, // Offset(238), PCIE LTR max no snoop Latency 9 Offset(240), PNLA, 16, // Offset(240), PCIE LTR max no snoop Latency 10 Offset(242), PNLB, 16, // Offset(242), PCIE LTR max no snoop Latency 11 Offset(244), PNLC, 16, // Offset(244), PCIE LTR max no snoop Latency 12 Offset(246), PNLD, 16, // Offset(246), PCIE LTR max no snoop Latency 13 Offset(248), PNLE, 16, // Offset(248), PCIE LTR max no snoop Latency 14 Offset(250), PNLF, 16, // Offset(250), PCIE LTR max no snoop Latency 15 Offset(252), PNLG, 16, // Offset(252), PCIE LTR max no snoop Latency 16 Offset(254), PNLH, 16, // Offset(254), PCIE LTR max no snoop Latency 17 Offset(256), PNLI, 16, // Offset(256), PCIE LTR max no snoop Latency 18 Offset(258), PNLJ, 16, // Offset(258), PCIE LTR max no snoop Latency 19 Offset(260), PNLK, 16, // Offset(260), PCIE LTR max no snoop Latency 20 Offset(262), PNLL, 16, // Offset(262), PCIE LTR max no snoop Latency 21 Offset(264), PNLM, 16, // Offset(264), PCIE LTR max no snoop Latency 22 Offset(266), PNLN, 16, // Offset(266), PCIE LTR max no snoop Latency 23 Offset(268), PNLO, 16, // Offset(268), PCIE LTR max no snoop Latency 24 Offset(270), PNLP, 16, // Offset(270), PCIE LTR max no snoop Latency 25 Offset(272), PNLQ, 16, // Offset(272), PCIE LTR max no snoop Latency 26 Offset(274), PNLR, 16, // Offset(274), PCIE LTR max no snoop Latency 27 Offset(276), PNLS, 16, // Offset(276), PCIE LTR max no snoop Latency 28 Offset(278), XHPC, 8, // Offset(278), Number of HighSpeed ports implemented in XHCI controller Offset(279), XRPC, 8, // Offset(279), Number of USBR ports implemented in XHCI controller Offset(280), XSPC, 8, // Offset(280), Number of SuperSpeed ports implemented in XHCI controller Offset(281), XSPA, 8, // Offset(281), Address of 1st SuperSpeed port Offset(282), HPTB, 32, // Offset(282), HPET base address Offset(286), HPTE, 8, // Offset(286), HPET enable //SerialIo block Offset(287), SM00, 8, // Offset(287), SerialIo SPI Controller 0 Mode Offset(288), SM01, 8, // Offset(288), SerialIo SPI Controller 1 Mode Offset(289), SM02, 8, // Offset(289), SerialIo SPI Controller 2 Mode Offset(290), SM03, 8, // Offset(290), SerialIo SPI Controller 3 Mode Offset(291), SM04, 8, // Offset(291), SerialIo SPI Controller 4 Mode Offset(292), SM05, 8, // Offset(292), SerialIo SPI Controller 5 Mode Offset(293), SM06, 8, // Offset(293), SerialIo SPI Controller 6 Mode Offset(294), SC00, 64, // Offset(294), SerialIo SPI Controller 0 Pci Config Offset(302), SC01, 64, // Offset(302), SerialIo SPI Controller 1 Pci Config Offset(310), SC02, 64, // Offset(310), SerialIo SPI Controller 2 Pci Config Offset(318), SC03, 64, // Offset(318), SerialIo SPI Controller 3 Pci Config Offset(326), SC04, 64, // Offset(326), SerialIo SPI Controller 4 Pci Config Offset(334), SC05, 64, // Offset(334), SerialIo SPI Controller 5 Pci Config Offset(342), SC06, 64, // Offset(342), SerialIo SPI Controller 6 Pci Config Offset(350), IM00, 8, // Offset(350), SerialIo I2C Controller 0 Mode Offset(351), IM01, 8, // Offset(351), SerialIo I2C Controller 1 Mode Offset(352), IM02, 8, // Offset(352), SerialIo I2C Controller 2 Mode Offset(353), IM03, 8, // Offset(353), SerialIo I2C Controller 3 Mode Offset(354), IM04, 8, // Offset(354), SerialIo I2C Controller 4 Mode Offset(355), IM05, 8, // Offset(355), SerialIo I2C Controller 5 Mode Offset(356), IM06, 8, // Offset(356), SerialIo I2C Controller 6 Mode Offset(357), IM07, 8, // Offset(357), SerialIo I2C Controller 7 Mode Offset(358), IC00, 64, // Offset(358), SerialIo I2C Controller 0 Pci Config Offset(366), IC01, 64, // Offset(366), SerialIo I2C Controller 1 Pci Config Offset(374), IC02, 64, // Offset(374), SerialIo I2C Controller 2 Pci Config Offset(382), IC03, 64, // Offset(382), SerialIo I2C Controller 3 Pci Config Offset(390), IC04, 64, // Offset(390), SerialIo I2C Controller 4 Pci Config Offset(398), IC05, 64, // Offset(398), SerialIo I2C Controller 5 Pci Config Offset(406), IC06, 64, // Offset(406), SerialIo I2C Controller 6 Pci Config Offset(414), IC07, 64, // Offset(414), SerialIo I2C Controller 7 Pci Config Offset(422), UM00, 8, // Offset(422), SerialIo UART Controller 0 Mode Offset(423), UM01, 8, // Offset(423), SerialIo UART Controller 1 Mode Offset(424), UM02, 8, // Offset(424), SerialIo UART Controller 2 Mode Offset(425), UM03, 8, // Offset(425), SerialIo UART Controller 3 Mode Offset(426), UM04, 8, // Offset(426), SerialIo UART Controller 4 Mode Offset(427), UM05, 8, // Offset(427), SerialIo UART Controller 5 Mode Offset(428), UM06, 8, // Offset(428), SerialIo UART Controller 6 Mode Offset(429), UC00, 64, // Offset(429), SerialIo UART Controller 0 Pci Config Offset(437), UC01, 64, // Offset(437), SerialIo UART Controller 1 Pci Config Offset(445), UC02, 64, // Offset(445), SerialIo UART Controller 2 Pci Config Offset(453), UC03, 64, // Offset(453), SerialIo UART Controller 3 Pci Config Offset(461), UC04, 64, // Offset(461), SerialIo UART Controller 4 Pci Config Offset(469), UC05, 64, // Offset(469), SerialIo UART Controller 5 Pci Config Offset(477), UC06, 64, // Offset(477), SerialIo UART Controller 6 Pci Config Offset(485), UD00, 8, // Offset(485), SerialIo UART Controller 0 DmaEnable Offset(486), UD01, 8, // Offset(486), SerialIo UART Controller 1 DmaEnable Offset(487), UD02, 8, // Offset(487), SerialIo UART Controller 2 DmaEnable Offset(488), UD03, 8, // Offset(488), SerialIo UART Controller 3 DmaEnable Offset(489), UD04, 8, // Offset(489), SerialIo UART Controller 4 DmaEnable Offset(490), UD05, 8, // Offset(490), SerialIo UART Controller 5 DmaEnable Offset(491), UD06, 8, // Offset(491), SerialIo UART Controller 6 DmaEnable Offset(492), UP00, 8, // Offset(492), SerialIo UART Controller 0 Power Gating Offset(493), UP01, 8, // Offset(493), SerialIo UART Controller 1 Power Gating Offset(494), UP02, 8, // Offset(494), SerialIo UART Controller 2 Power Gating Offset(495), UP03, 8, // Offset(495), SerialIo UART Controller 3 Power Gating Offset(496), UP04, 8, // Offset(496), SerialIo UART Controller 4 Power Gating Offset(497), UP05, 8, // Offset(497), SerialIo UART Controller 5 Power Gating Offset(498), UP06, 8, // Offset(498), SerialIo UART Controller 6 Power Gating Offset(499), UI00, 8, // Offset(499), SerialIo UART Controller 0 Irq Offset(500), UI01, 8, // Offset(500), SerialIo UART Controller 1 Irq Offset(501), UI02, 8, // Offset(501), SerialIo UART Controller 2 Irq Offset(502), UI03, 8, // Offset(502), SerialIo UART Controller 3 Irq Offset(503), UI04, 8, // Offset(503), SerialIo UART Controller 4 Irq Offset(504), UI05, 8, // Offset(504), SerialIo UART Controller 5 Irq Offset(505), UI06, 8, // Offset(505), SerialIo UART Controller 6 Irq //end of SerialIo block Offset(506), SGIR, 8, // Offset(506), GPIO IRQ Offset(507), GPHD, 8, // Offset(507), Hide GPIO ACPI device Offset(508), NIT1, 8, // Offset(508), RST PCIe Storage Cycle Router#1 Interface Type Offset(509), NIT2, 8, // Offset(509), RST PCIe Storage Cycle Router#2 Interface Type Offset(510), NIT3, 8, // Offset(510), RST PCIe Storage Cycle Router#3 Interface Type Offset(511), NPM1, 8, // Offset(511), RST PCIe Storage Cycle Router#1 Power Management Capability Pointer Offset(512), NPM2, 8, // Offset(512), RST PCIe Storage Cycle Router#2 Power Management Capability Pointer Offset(513), NPM3, 8, // Offset(513), RST PCIe Storage Cycle Router#3 Power Management Capability Pointer Offset(514), NPC1, 8, // Offset(514), RST PCIe Storage Cycle Router#1 PCIe Capabilities Pointer Offset(515), NPC2, 8, // Offset(515), RST PCIe Storage Cycle Router#2 PCIe Capabilities Pointer Offset(516), NPC3, 8, // Offset(516), RST PCIe Storage Cycle Router#3 PCIe Capabilities Pointer Offset(517), NL11, 16, // Offset(517), RST PCIe Storage Cycle Router#1 L1SS Capability Pointer Offset(519), NL12, 16, // Offset(519), RST PCIe Storage Cycle Router#2 L1SS Capability Pointer Offset(521), NL13, 16, // Offset(521), RST PCIe Storage Cycle Router#3 L1SS Capability Pointer Offset(523), ND21, 8, // Offset(523), RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data2 Offset(524), ND22, 8, // Offset(524), RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data2 Offset(525), ND23, 8, // Offset(525), RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data2 Offset(526), ND11, 32, // Offset(526), RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data1 Offset(530), ND12, 32, // Offset(530), RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data1 Offset(534), ND13, 32, // Offset(534), RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data1 Offset(538), NLR1, 16, // Offset(538), RST PCIe Storage Cycle Router#1 LTR Capability Pointer Offset(540), NLR2, 16, // Offset(540), RST PCIe Storage Cycle Router#2 LTR Capability Pointer Offset(542), NLR3, 16, // Offset(542), RST PCIe Storage Cycle Router#3 LTR Capability Pointer Offset(544), NLD1, 32, // Offset(544), RST PCIe Storage Cycle Router#1 Endpoint LTR Data Offset(548), NLD2, 32, // Offset(548), RST PCIe Storage Cycle Router#2 Endpoint LTR Data Offset(552), NLD3, 32, // Offset(552), RST PCIe Storage Cycle Router#3 Endpoint LTR Data Offset(556), NEA1, 16, // Offset(556), RST PCIe Storage Cycle Router#1 Endpoint LCTL Data Offset(558), NEA2, 16, // Offset(558), RST PCIe Storage Cycle Router#2 Endpoint LCTL Data Offset(560), NEA3, 16, // Offset(560), RST PCIe Storage Cycle Router#3 Endpoint LCTL Data Offset(562), NEB1, 16, // Offset(562), RST PCIe Storage Cycle Router#1 Endpoint DCTL Data Offset(564), NEB2, 16, // Offset(564), RST PCIe Storage Cycle Router#2 Endpoint DCTL Data Offset(566), NEB3, 16, // Offset(566), RST PCIe Storage Cycle Router#3 Endpoint DCTL Data Offset(568), NEC1, 16, // Offset(568), RST PCIe Storage Cycle Router#1 Endpoint DCTL2 Data Offset(570), NEC2, 16, // Offset(570), RST PCIe Storage Cycle Router#2 Endpoint DCTL2 Data Offset(572), NEC3, 16, // Offset(572), RST PCIe Storage Cycle Router#3 Endpoint DCTL2 Data Offset(574), NRA1, 16, // Offset(574), RST PCIe Storage Cycle Router#1 RootPort DCTL2 Data Offset(576), NRA2, 16, // Offset(576), RST PCIe Storage Cycle Router#2 RootPort DCTL2 Data Offset(578), NRA3, 16, // Offset(578), RST PCIe Storage Cycle Router#3 RootPort DCTL2 Data Offset(580), NMB1, 32, // Offset(580), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR Offset(584), NMB2, 32, // Offset(584), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR Offset(588), NMB3, 32, // Offset(588), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR Offset(592), NMV1, 32, // Offset(592), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR value Offset(596), NMV2, 32, // Offset(596), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR value Offset(600), NMV3, 32, // Offset(600), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR value Offset(604), NPB1, 32, // Offset(604), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR Offset(608), NPB2, 32, // Offset(608), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR Offset(612), NPB3, 32, // Offset(612), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR Offset(616), NPV1, 32, // Offset(616), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR value Offset(620), NPV2, 32, // Offset(620), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR value Offset(624), NPV3, 32, // Offset(624), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR value Offset(628), NRP1, 32, // Offset(628), RST PCIe Storage Cycle Router#1 Root Port number Offset(632), NRP2, 32, // Offset(632), RST PCIe Storage Cycle Router#2 Root Port number Offset(636), NRP3, 32, // Offset(636), RST PCIe Storage Cycle Router#3 Root Port number Offset(640), EMH4, 8, // Offset(640), eMMC HS400 mode enabled Offset(641), EMDS, 8, // Offset(641), eMMC Driver Strength Offset(642), CSKU, 8, // Offset(642), CPU SKU Offset(643), ITA0, 16, // Offset(643), Offset(645), ITA1, 16, // Offset(645), Offset(647), ITA2, 16, // Offset(647), Offset(649), ITA3, 16, // Offset(649), Offset(651), ITS0, 8, // Offset(651), Offset(652), ITS1, 8, // Offset(652), Offset(653), ITS2, 8, // Offset(653), Offset(654), ITS3, 8, // Offset(654), Offset(655), PMBS, 16, // Offset(655), ACPI IO BASE address Offset(657), PWRM, 32, // Offset(657), PWRM MEM BASE address // CNVi specific Offset(661), CNVI, 8, // Offset(661), CNVi mode Offset(662), CBTC, 8, // Offset(662), CNVi BT Core Offset(663), CBTA, 8, // Offset(663), CNVi BT Audio Offload Offset(664), CVPR, 8, // Offset(664), CNVi vPro Offset(665), CRFI, 8, // Offset(665), CNVi DDR RFI Mitigation Offset(666), CRFP, 8, // Offset(666), CNVi CRF present // PCH Trace Hub Offset(667), PTHM, 8, // Offset(667), PCH Trace Hub Mode // PCH PS_ON support Offset(668), PSON, 8, // Offset(668), PCH PS_ON enable // // These are for PchApciTablesSelfTest use // Offset(669), LTR1, 8, // Offset(669), Latency Tolerance Reporting Enable Offset(670), LTR2, 8, // Offset(670), Latency Tolerance Reporting Enable Offset(671), LTR3, 8, // Offset(671), Latency Tolerance Reporting Enable Offset(672), LTR4, 8, // Offset(672), Latency Tolerance Reporting Enable Offset(673), LTR5, 8, // Offset(673), Latency Tolerance Reporting Enable Offset(674), LTR6, 8, // Offset(674), Latency Tolerance Reporting Enable Offset(675), LTR7, 8, // Offset(675), Latency Tolerance Reporting Enable Offset(676), LTR8, 8, // Offset(676), Latency Tolerance Reporting Enable Offset(677), LTR9, 8, // Offset(677), Latency Tolerance Reporting Enable Offset(678), LTRA, 8, // Offset(678), Latency Tolerance Reporting Enable Offset(679), LTRB, 8, // Offset(679), Latency Tolerance Reporting Enable Offset(680), LTRC, 8, // Offset(680), Latency Tolerance Reporting Enable Offset(681), LTRD, 8, // Offset(681), Latency Tolerance Reporting Enable Offset(682), LTRE, 8, // Offset(682), Latency Tolerance Reporting Enable Offset(683), LTRF, 8, // Offset(683), Latency Tolerance Reporting Enable Offset(684), LTRG, 8, // Offset(684), Latency Tolerance Reporting Enable Offset(685), LTRH, 8, // Offset(685), Latency Tolerance Reporting Enable Offset(686), LTRI, 8, // Offset(686), Latency Tolerance Reporting Enable Offset(687), LTRJ, 8, // Offset(687), Latency Tolerance Reporting Enable Offset(688), LTRK, 8, // Offset(688), Latency Tolerance Reporting Enable Offset(689), LTRL, 8, // Offset(689), Latency Tolerance Reporting Enable Offset(690), LTRM, 8, // Offset(690), Latency Tolerance Reporting Enable Offset(691), LTRN, 8, // Offset(691), Latency Tolerance Reporting Enable Offset(692), LTRO, 8, // Offset(692), Latency Tolerance Reporting Enable Offset(693), LTRP, 8, // Offset(693), Latency Tolerance Reporting Enable Offset(694), LTRQ, 8, // Offset(694), Latency Tolerance Reporting Enable Offset(695), LTRR, 8, // Offset(695), Latency Tolerance Reporting Enable Offset(696), LTRS, 8, // Offset(696), Latency Tolerance Reporting Enable Offset(697), GBES, 8, // Offset(697), GbE Support Offset(698), PPDS, 32, // Offset(698), PCH xDCI Power Down Scale Value, DWC_USB3_GCTL_INIT[31:19] Offset(702), EMCE, 8, // Offset(702), Set to indicate that eMMC is enabled Offset(703), SDCE, 8, // Offset(703), Set to indicate that SD card is enabled Offset(704), TGEA, 8, // Offset(704), Set to indicate that Timed GPIO 0 is enabled Offset(705), TGEB, 8, // Offset(705), Set to indicate that Timed GPIO 1 is enabled Offset(706), CR00, 8, // Offset(706), CLOCK index to root port index map. Used during PCIe D3Cold flows Offset(707), CR01, 8, // Offset(707), Offset(708), CR02, 8, // Offset(708), Offset(709), CR03, 8, // Offset(709), Offset(710), CR04, 8, // Offset(710), Offset(711), CR05, 8, // Offset(711), Offset(712), CR06, 8, // Offset(712), Offset(713), CR07, 8, // Offset(713), Offset(714), CR08, 8, // Offset(714), Offset(715), CR09, 8, // Offset(715), Offset(716), CR10, 8, // Offset(716), Offset(717), CR11, 8, // Offset(717), Offset(718), CR12, 8, // Offset(718), Offset(719), CR13, 8, // Offset(719), Offset(720), CR14, 8, // Offset(720), Offset(721), CR15, 8, // Offset(721), Offset(722), CR16, 8, // Offset(722), Offset(723), CR17, 8, // Offset(723), Offset(724), TCOB, 16, // Offset(724), TCO base address Offset(726), ICKP, 16, // Offset(726), Iclk PID number Offset(728), PCNV, 16, // Offset(728), CNVi sideband port id Offset(730), HBSL, 32, // Offset(730), Offset(734), PU2C, 8, // Offset(734), Number of USB2 ports in PCH Offset(735), PU3C, 8, // Offset(735), Number of USB3 ports in PCH Offset(736), SPPR, 8, // Offset(736), Holds information from SATA PCS register about SATA ports which recieved COMINIT from connected devices. Offset(737), IPCC, 8, // Offset(737), PCIE CLKREQ IPC command support Offset(738), CQ00, 8, // Offset(738), CLOCK Source index to ClkReq Number. Used during PCIe D3Cold flows Offset(739), CQ01, 8, // Offset(739), Offset(740), CQ02, 8, // Offset(740), Offset(741), CQ03, 8, // Offset(741), Offset(742), CQ04, 8, // Offset(742), Offset(743), CQ05, 8, // Offset(743), Offset(744), CQ06, 8, // Offset(744), Offset(745), CQ07, 8, // Offset(745), Offset(746), CQ08, 8, // Offset(746), Offset(747), CQ09, 8, // Offset(747), Offset(748), CQ10, 8, // Offset(748), Offset(749), CQ11, 8, // Offset(749), Offset(750), CQ12, 8, // Offset(750), Offset(751), CQ13, 8, // Offset(751), Offset(752), CQ14, 8, // Offset(752), Offset(753), CQ15, 8, // Offset(753), Offset(754), CQ16, 8, // Offset(754), Offset(755), CQ17, 8, // Offset(755), Offset(756), TIN0, 32, // Offset(756), Touch Host Controller Wake On Touch Interrupt Number - when 0 wake is disabled Offset(760), TIN1, 32, // Offset(760), Offset(764), TMD0, 16, // Offset(764), Touch Host Controller Mode THC or HID over SPI Offset(766), TMD1, 16, // Offset(766), Offset(768), UF0E, 8, // Offset(768), Is UFS0 Enabled Offset(769), UF1E, 8, // Offset(769), Is UFS1 Enabled Offset(770), UAOE, 8, // Offset(770), Is USB Audio Offload enabled Offset(771), T010, 32, // Offset(771), Touch Host Controller HID over SPI Reset Pad Offset(775), T011, 32, // Offset(775), Offset(779), T020, 8, // Offset(779), Touch Host Controller HID over SPI Reset Pad Trigger Offset(780), T021, 8, // Offset(780), Offset(781), T030, 32, // Offset(781), Touch Host Controller HID over SPI Connection Speed Offset(785), T031, 32, // Offset(785), Offset(789), T040, 32, // Offset(789), Touch Host Controller HID over SPI Input Report Header Address Offset(793), T041, 32, // Offset(793), Offset(797), T050, 32, // Offset(797), Touch Host Controller HID over SPI Input Report Body Address Offset(801), T051, 32, // Offset(801), Offset(805), T060, 32, // Offset(805), Touch Host Controller HID over SPI Output Report Address Offset(809), T061, 32, // Offset(809), Offset(813), T070, 32, // Offset(813), Touch Host Controller HID over SPI Read Opcode Offset(817), T071, 32, // Offset(817), Offset(821), T080, 32, // Offset(821), Touch Host Controller HID over SPI Write Opcode Offset(825), T081, 32, // Offset(825), Offset(829), T090, 32, // Offset(829), Touch Host Controller HID over SPI Flags Offset(833), T091, 32, // Offset(833), Offset(837), T0A0, 32, // Offset(837), Touch Host Controller Active Ltr Offset(841), T0A1, 32, // Offset(841), Offset(845), T0B0, 32, // Offset(845), Touch Host Controller Idle Ltr Offset(849), T0B1, 32, // Offset(849), Offset(853), T0C0, 32, // Offset(853), Touch Host Controller HID over SPI Limit Packet Size Offset(857), T0C1, 32, // Offset(857), Offset(861), T0D0, 32, // Offset(861), Touch Host Controller HID over SPI Performance Limitation Offset(865), T0D1, 32, // Offset(865), Offset(869), HBCL, 32, // Offset(869), Cpu Root port used for hybrid storage Offset(873), HBPL, 32, // Offset(873), Pch Root port used for hybrid storage Offset(877), AL6D, 32, // Offset(877), _L6D Enable, BIOS-ACPI can verify PMEENABLE and PMESTATUS of each device that requires GPE related wake }