//
// Automatically generated by GenNvs ver 2.4.6
// Please DO NOT modify !!!
//
/**@file
@copyright
INTEL CONFIDENTIAL
Copyright 2016 - 2021 Intel Corporation.
The source code contained or described herein and all documents related to the
source code ("Material") are owned by Intel Corporation or its suppliers or
licensors. Title to the Material remains with Intel Corporation or its suppliers
and licensors. The Material may contain trade secrets and proprietary and
confidential information of Intel Corporation and its suppliers and licensors,
and is protected by worldwide copyright and trade secret laws and treaty
provisions. No part of the Material may be used, copied, reproduced, modified,
published, uploaded, posted, transmitted, distributed, or disclosed in any way
without Intel's prior express written permission.
No license under any patent, copyright, trade secret or other intellectual
property right is granted to or conferred upon you by disclosure or delivery
of the Materials, either expressly, by implication, inducement, estoppel or
otherwise. Any license under such intellectual property rights must be
express and approved by Intel in writing.
Unless otherwise agreed by Intel in writing, you may not remove or alter
this notice or any other notice embedded in Materials by Intel or
Intel's suppliers or licensors in any way.
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
the terms of your license agreement with Intel or your vendor. This file may
be modified by the user, subject to additional terms of the license agreement.
@par Specification Reference:
**/
//
// Define SA NVS Area operation region.
//
#ifndef _SA_NVS_AREA_DEF_H_
#define _SA_NVS_AREA_DEF_H_
#pragma pack (push,1)
typedef struct {
UINT32 IgdOpRegionAddress; ///< Offset 0 IGD OpRegion base address
UINT8 GfxTurboIMON; ///< Offset 4 IMON Current Value
UINT8 IgdState; ///< Offset 5 IGD State (Primary Display = 1)
UINT8 IgdBootType; ///< Offset 6 IGD Boot Display Device
UINT8 IgdPanelType; ///< Offset 7 IGD Panel Type CMOS option
UINT8 IgdPanelScaling; ///< Offset 8 IGD Panel Scaling
UINT8 IgdBiaConfig; ///< Offset 9 IGD BIA Configuration
UINT8 IgdSscConfig; ///< Offset 10 IGD SSC Configuration
UINT8 IgdFunc1Enable; ///< Offset 11 IGD Function 1 Enable
UINT8 IgdHpllVco; ///< Offset 12 HPLL VCO
UINT8 IgdSciSmiMode; ///< Offset 13 GMCH SMI/SCI mode (0=SCI)
UINT8 IgdPAVP; ///< Offset 14 IGD PAVP data
UINT8 CurrentDeviceList; ///< Offset 15 Current Attached Device List
UINT16 CurrentDisplayState; ///< Offset 16 Current Display State
UINT16 NextDisplayState; ///< Offset 18 Next Display State
UINT8 NumberOfValidDeviceId; ///< Offset 20 Number of Valid Device IDs
UINT32 DeviceId1; ///< Offset 21 Device ID 1
UINT32 DeviceId2; ///< Offset 25 Device ID 2
UINT32 DeviceId3; ///< Offset 29 Device ID 3
UINT32 DeviceId4; ///< Offset 33 Device ID 4
UINT32 DeviceId5; ///< Offset 37 Device ID 5
UINT32 DeviceId6; ///< Offset 41 Device ID 6
UINT32 DeviceId7; ///< Offset 45 Device ID 7
UINT32 DeviceId8; ///< Offset 49 Device ID 8
UINT32 DeviceId9; ///< Offset 53 Device ID 9
UINT32 DeviceId10; ///< Offset 57 Device ID 10
UINT32 DeviceId11; ///< Offset 61 Device ID 11
UINT32 DeviceId12; ///< Offset 65 Device ID 12
UINT32 DeviceId13; ///< Offset 69 Device ID 13
UINT32 DeviceId14; ///< Offset 73 Device ID 14
UINT32 DeviceId15; ///< Offset 77 Device ID 15
UINT32 DeviceIdX; ///< Offset 81 Device ID for eDP device
UINT32 NextStateDid1; ///< Offset 85 Next state DID1 for _DGS
UINT32 NextStateDid2; ///< Offset 89 Next state DID2 for _DGS
UINT32 NextStateDid3; ///< Offset 93 Next state DID3 for _DGS
UINT32 NextStateDid4; ///< Offset 97 Next state DID4 for _DGS
UINT32 NextStateDid5; ///< Offset 101 Next state DID5 for _DGS
UINT32 NextStateDid6; ///< Offset 105 Next state DID6 for _DGS
UINT32 NextStateDid7; ///< Offset 109 Next state DID7 for _DGS
UINT32 NextStateDid8; ///< Offset 113 Next state DID8 for _DGS
UINT32 NextStateDidEdp; ///< Offset 117 Next state DID for eDP
UINT8 LidState; ///< Offset 121 Lid State (Lid Open = 1)
UINT32 AKsv0; ///< Offset 122 First four bytes of AKSV (manufacturing mode)
UINT8 AKsv1; ///< Offset 126 Fifth byte of AKSV (manufacturing mode)
UINT8 BrightnessPercentage; ///< Offset 127 Brightness Level Percentage
UINT8 AlsEnable; ///< Offset 128 Ambient Light Sensor Enable
UINT8 AlsAdjustmentFactor; ///< Offset 129 Ambient Light Adjusment Factor
UINT8 LuxLowValue; ///< Offset 130 LUX Low Value
UINT8 LuxHighValue; ///< Offset 131 LUX High Value
UINT8 ActiveLFP; ///< Offset 132 Active LFP
UINT8 IpuAcpiMode; ///< Offset 133 IPU ACPI device type (0=Disabled, 1=AVStream virtual device as child of GFX)
UINT8 EdpValid; ///< Offset 134 Check for eDP display device
UINT8 HgMode; ///< Offset 135 SG Mode (0=Disabled, 1=HG Muxed, 2=HG Muxless, 3=DGPU Only)
UINT8 HgFeatureList; ///< Offset 136 HG Feature List
UINT8 Pcie0GpioSupport; ///< Offset 137 PCIe0 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
UINT8 Pcie0HoldRstExpanderNo; ///< Offset 138 PCIe0 HLD RST IO Expander Number
UINT32 Pcie0HoldRstGpioNo; ///< Offset 139 PCIe0 HLD RST GPIO Number
UINT8 Pcie0HoldRstActiveInfo; ///< Offset 143 PCIe0 HLD RST GPIO Active Information
UINT8 Pcie0PwrEnExpanderNo; ///< Offset 144 PCIe0 PWR Enable IO Expander Number
UINT32 Pcie0PwrEnGpioNo; ///< Offset 145 PCIe0 PWR Enable GPIO Number
UINT8 Pcie0PwrEnActiveInfo; ///< Offset 149 PCIe0 PWR Enable GPIO Active Information
UINT8 Pcie1GpioSupport; ///< Offset 150 PCIe1 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
UINT8 Pcie1HoldRstExpanderNo; ///< Offset 151 PCIe1 HLD RST IO Expander Number
UINT32 Pcie1HoldRstGpioNo; ///< Offset 152 PCIe1 HLD RST GPIO Number
UINT8 Pcie1HoldRstActiveInfo; ///< Offset 156 PCIe1 HLD RST GPIO Active Information
UINT8 Pcie1PwrEnExpanderNo; ///< Offset 157 PCIe1 PWR Enable IO Expander Number
UINT32 Pcie1PwrEnGpioNo; ///< Offset 158 PCIe1 PWR Enable GPIO Number
UINT8 Pcie1PwrEnActiveInfo; ///< Offset 162 PCIe1 PWR Enable GPIO Active Information
UINT8 Pcie2GpioSupport; ///< Offset 163 PCIe2 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
UINT8 Pcie2HoldRstExpanderNo; ///< Offset 164 PCIe2 HLD RST IO Expander Number
UINT32 Pcie2HoldRstGpioNo; ///< Offset 165 PCIe2 HLD RST GPIO Number
UINT8 Pcie2HoldRstActiveInfo; ///< Offset 169 PCIe2 HLD RST GPIO Active Information
UINT8 Pcie2PwrEnExpanderNo; ///< Offset 170 PCIe2 PWR Enable IO Expander Number
UINT32 Pcie2PwrEnGpioNo; ///< Offset 171 PCIe2 PWR Enable GPIO Number
UINT8 Pcie2PwrEnActiveInfo; ///< Offset 175 PCIe2 PWR Enable GPIO Active Information
UINT8 Pcie3GpioSupport; ///< Offset 176 PCIe3 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
UINT8 Pcie3HoldRstExpanderNo; ///< Offset 177 PCIe3 HLD RST IO Expander Number
UINT32 Pcie3HoldRstGpioNo; ///< Offset 178 PCIe3 HLD RST GPIO Number
UINT8 Pcie3HoldRstActiveInfo; ///< Offset 182 PCIe3 HLD RST GPIO Active Information
UINT8 Pcie3PwrEnExpanderNo; ///< Offset 183 PCIe3 PWR Enable IO Expander Number
UINT32 Pcie3PwrEnGpioNo; ///< Offset 184 PCIe3 PWR Enable GPIO Number
UINT8 Pcie3PwrEnActiveInfo; ///< Offset 188 PCIe3 PWR Enable GPIO Active Information
UINT32 Pcie3WakeGpioNo; ///< Offset 189 PCIe3 RTD3 Device Wake GPIO Number
UINT16 DelayAfterPwrEn; ///< Offset 193 Delay after power enable for PCIe
UINT16 DelayAfterHoldReset; ///< Offset 195 Delay after Hold Reset for PCIe
UINT8 Pcie0EpCapOffset; ///< Offset 197 PCIe0 Endpoint Capability Structure Offset
UINT32 XPcieCfgBaseAddress; ///< Offset 198 Any Device's PCIe Config Space Base Address
UINT16 GpioBaseAddress; ///< Offset 202 GPIO Base Address
UINT32 NvIgOpRegionAddress; ///< Offset 204 NVIG opregion address
UINT32 NvHmOpRegionAddress; ///< Offset 208 NVHM opregion address
UINT32 ApXmOpRegionAddress; ///< Offset 212 AMDA opregion address
UINT8 Peg0LtrEnable; ///< Offset 216 Latency Tolerance Reporting Enable
UINT8 Peg0ObffEnable; ///< Offset 217 Optimized Buffer Flush and Fill
UINT8 Peg1LtrEnable; ///< Offset 218 Latency Tolerance Reporting Enable
UINT8 Peg1ObffEnable; ///< Offset 219 Optimized Buffer Flush and Fill
UINT8 Peg2LtrEnable; ///< Offset 220 Latency Tolerance Reporting Enable
UINT8 Peg2ObffEnable; ///< Offset 221 Optimized Buffer Flush and Fill
UINT8 Peg3LtrEnable; ///< Offset 222 Latency Tolerance Reporting Enable
UINT8 Peg3ObffEnable; ///< Offset 223 Optimized Buffer Flush and Fill
UINT16 PegLtrMaxSnoopLatency; ///< Offset 224 SA Peg Latency Tolerance Reporting Max Snoop Latency
UINT16 PegLtrMaxNoSnoopLatency; ///< Offset 226 SA Peg Latency Tolerance Reporting Max No Snoop Latency
UINT64 Mmio64Base; ///< Offset 228 Base of above 4GB MMIO resource
UINT64 Mmio64Length; ///< Offset 236 Length of above 4GB MMIO resource
UINT32 CpuIdInfo; ///< Offset 244 CPU ID info to get Family Id or Stepping
UINT32 Mmio32Base; ///< Offset 248 Base of below 4GB MMIO resource
UINT32 Mmio32Length; ///< Offset 252 Length of below 4GB MMIO resource
UINT32 Pcie0WakeGpioNo; ///< Offset 256 PCIe0 RTD3 Device Wake GPIO Number
UINT32 Pcie1WakeGpioNo; ///< Offset 260 PCIe1 RTD3 Device Wake GPIO Number
UINT32 Pcie2WakeGpioNo; ///< Offset 264 PCIe2 RTD3 Device Wake GPIO Number
UINT8 VtdDisable; ///< Offset 268 VT-d Enable/Disable
UINT32 VtdBaseAddress[7]; ///< Offset 269 VT-d Base Address 1
///< Offset 273 VT-d Base Address 2
///< Offset 277 VT-d Base Address 3
///< Offset 281 VT-d Base Address 4 (iTBT PCIE0)
///< Offset 285 VT-d Base Address 5 (iTBT PCIE1)
///< Offset 289 VT-d Base Address 6 (iTBT PCIE2)
///< Offset 293 VT-d Base Address 7 (iTBT PCIE3)
UINT16 VtdEngine1Vid; ///< Offset 297 VT-d Engine#1 Vendor ID
UINT16 VtdEngine2Vid; ///< Offset 299 VT-d Engine#2 Vendor ID
UINT8 RootPortIndex; ///< Offset 301 RootPort Number
UINT32 RootPortAddress; ///< Offset 302 RootPortAddress
UINT8 CpuTraceHubMode; ///< Offset 306 CPU Trace Hub Mode
UINT8 SimicsEnvironment; ///< Offset 307 Simics Environment information
UINT8 ItbtXhciEn; ///< Offset 308 TCSS XHCI Device Enable
UINT8 ItbtXdciEn; ///< Offset 309 TCSS XDCI Device Enable
UINT8 ItbtDmaEn[2]; ///< Offset 310 TCSS DMA 0 Device Enable
///< Offset 311 TCSS DMA 1 Device Enable
UINT8 ItbtPcieRpEn[4]; ///< Offset 312 TCSS ItbtPcieRp PCIE RP 0 Device Enable
///< Offset 313 TCSS ItbtPcieRp PCIE RP 1 Device Enable
///< Offset 314 TCSS ItbtPcieRp PCIE RP 2 Device Enable
///< Offset 315 TCSS ItbtPcieRp PCIE RP 3 Device Enable
UINT32 ItbtPcieRpAddress[4]; ///< Offset 316 TCSS ItbtPcie Root Port address 0
///< Offset 320 TCSS ItbtPcie Root Port address 1
///< Offset 324 TCSS ItbtPcie Root Port address 2
///< Offset 328 TCSS ItbtPcie Root Port address 3
UINT32 TcssxDCIPwrDnScale; ///< Offset 332 TCSS xDCI Power Down Scale Value, DWC_USB3_GCTL_INIT[31:19]
UINT8 TcssxDCIInt; ///< Offset 336 TCSS xDCI Int Pin
UINT8 TcssxDCIIrq; ///< Offset 337 TCSS xDCI Irq Number
UINT8 TcssRtd3; ///< Offset 338 TCSS RTD3
UINT32 TcssDma0RmrrAddr; ///< Offset 339 TCSS DMA0 RMRR address
UINT32 TcssDma1RmrrAddr; ///< Offset 343 TCSS DMA1 RMRR address
UINT8 LtrEnable[4]; ///< Offset 347 Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
///< Offset 348 Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
///< Offset 349 Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
///< Offset 350 Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
UINT16 PcieLtrMaxSnoopLatency[4]; ///< Offset 351 PCIE LTR max snoop Latency 0
///< Offset 353 PCIE LTR max snoop Latency 1
///< Offset 355 PCIE LTR max snoop Latency 2
///< Offset 357 PCIE LTR max snoop Latency 3
UINT16 PcieLtrMaxNoSnoopLatency[4]; ///< Offset 359 PCIE LTR max no snoop Latency 0
///< Offset 361 PCIE LTR max no snoop Latency 1
///< Offset 363 PCIE LTR max no snoop Latency 2
///< Offset 365 PCIE LTR max no snoop Latency 3
UINT8 IomReady; ///< Offset 367 IOM Ready
UINT8 TcssIomVccSt; ///< Offset 368 TCSS IOM VccSt
UINT8 CpuPcieRp0Enable; ///< Offset 369 <0:Disabled, 1:Enabled>
UINT8 CpuPcieRp1Enable; ///< Offset 370 <0:Disabled, 1:Enabled>
UINT8 CpuPcieRp2Enable; ///< Offset 371 <0:Disabled, 1:Enabled>
UINT8 CpuPcieRp3Enable; ///< Offset 372 <0:Disabled, 1:Enabled>
UINT8 VmdEnable; ///< Offset 373 VMD Device Enable
UINT32 DeviceIdY; ///< Offset 374 Device ID for second LFP device
UINT32 NextStateDidEdp2; ///< Offset 378 Next state DID for Second Display
UINT8 SlotSelection; ///< Offset 382 PCIe slot selection
UINT8 VmdRp1to8; ///< Offset 383 VMD PCH RP 1 to 8 mapped under VMD
UINT8 VmdRp9to16; ///< Offset 384 VMD PCH RP 9 to 16 mapped under VMD
UINT8 VmdRp17to24; ///< Offset 385 VMD PCH RP 17 to 24 mapped under VMD
UINT8 VmdRp25to32; ///< Offset 386 VMD PCH RP 25 to 32 mapped under VMD
UINT8 VmdSataPort0to7; ///< Offset 387 VMD SATA PORT 0 to 7 mapped under VMD
UINT8 VmdCpuRp; ///< Offset 388 VMD CPU RP mapped under VMD
UINT8 CpuPcieRtd3; ///< Offset 389 RTD3 Support for CPU PCIE.
UINT32 LaneUsed; ///< Offset 390 Lane Used of each CSI Port <0:Not Configured, 1:x1, 2:x2, 3:x3 4:x4>
UINT32 CsiSpeed; ///< Offset 394 Speed of each CSI Port <0:Not configured, 1:<416GMbps, 2:<1.5Gbps, 3:<2.0Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps>
UINT8 MaxPegPortNumber; ///< Offset 398 Max PEG port number
UINT8 MemBootMode; ///< Offset 399 Current Memory Boot Mode <0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION>
UINT8 DpmemSupport; ///< Offset 400 Dynamic PMem Support <0: Disabled, 1:Enabled>
UINT64 PmemStartingAddress; ///< Offset 401 Private Pmem Starting address
UINT64 PmemRangeLength; ///< Offset 409 Private Pmem Range Length
UINT8 IsBridgeDeviceBehindPeg1; ///< Offset 417 Is bridge device behind Peg1
UINT8 IsBridgeDeviceBehindPeg2; ///< Offset 418 Is bridge device behind Peg2
UINT8 IsBridgeDeviceBehindPeg3; ///< Offset 419 Is bridge device behind Peg3
UINT32 CpuPcieRpAddress[4]; ///< Offset 420 CpuPcieRp Address 1
///< Offset 424 CpuPcieRp address 2
///< Offset 428 CpuPcieRp address 3
///< Offset 432 CpuPcieRp Address 4
UINT16 RegBarOffset; ///< Offset 436 MCH RegBar Offset
} SYSTEM_AGENT_NVS_AREA;
#pragma pack(pop)
#endif