## @file
#  Alderlake S Pcie Clock configuration file.
#
# @copyright
#  INTEL CONFIDENTIAL
#  Copyright 2020 - 2021 Intel Corporation.
#
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#  source code ("Material") are owned by Intel Corporation or its suppliers or
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#  Unless otherwise agreed by Intel in writing, you may not remove or alter
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#
#  This file contains a 'Sample Driver' and is licensed as such under the terms
#  of your license agreement with Intel or your vendor. This file may be modified
#  by the user, subject to the additional terms of the license agreement.
#
# @par Specification
##

[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5UDimm1DAep]
gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
{{
  PCIE_PEG + 1,    // 1x16 PEG slot
  NOT_USED,
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 6,    // LAN Foxville
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 7,    // M.2 Key E WLAN
  PCIE_PCH + 20,  // Maple Ridge (BP)
  PCIE_PEG,       // M.2 Key M PEG Slot
  PCIE_PCH + 12,  // M.2 Socket3 Key M SSD 1
  PCIE_PCH + 24,  // Maple Ridge (FP)
  PCIE_PCH + 8,   // EDSFF Hot Swappable Ruler storage
  NOT_USED,
  NOT_USED,
  NOT_USED
}}
)}

[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5UDimm1DCrb]
gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
{{
  PCIE_PEG + 1,
  NOT_USED,
  PCIE_PCH + 20,  // PCIE x4 Slot 1
  NOT_USED,
  NOT_USED,
  LAN_CLOCK,
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 7,   // M.2_WLAN
  PCIE_PCH,       // M.2_SSD_3
  PCIE_PEG,       // CPU_M.2_SSD
  PCIE_PCH + 12,  // M.2_SSD
  PCIE_PCH + 24,  // M.2_SSD_2
  PCIE_PCH + 8,   // PCIE X4_SLOT_2
  PCIE_PCH + 4,    // PCIE X2_SLOT_3
  NOT_USED,
  NOT_USED
}}
)}

[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr4UDimm2DCrb]
gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
{{
  PCIE_PEG + 1,
  PCIE_PEG + 2,
  PCIE_PCH + 20,  // PCIE x4 Slot 1
  NOT_USED,
  NOT_USED,
  LAN_CLOCK,
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 7,   // M.2_WLAN
  PCIE_PCH,       // M.2_SSD_3
  PCIE_PEG,       // CPU_M.2_SSD
  PCIE_PCH + 12,  // M.2_SSD
  PCIE_PCH + 24,  // M.2_SSD_2
  PCIE_PCH + 8,   // PCIE X4_SLOT_2
  PCIE_PCH + 4,   // PCIE X2_SLOT_3
  NOT_USED,
  NOT_USED
}}
)}

[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr4SODimmCrb]
gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
{{
  PCIE_PEG + 1,
  NOT_USED,
  PCIE_PCH + 20,  // PCIE x4 Slot 1
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 6,   // Foxville
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 7,   // M.2_WLAN
  PCIE_PCH,       // M.2_SSD_3
  PCIE_PEG,       // CPU_M.2_SSD
  PCIE_PCH + 12,  // M.2_SSD
  PCIE_PCH + 24,  // Thunderbolt
  PCIE_PCH + 8,   // PCIE X4_SLOT_2
  PCIE_PCH + 4,    // PCIE X2_SLOT_3
  NOT_USED,
  NOT_USED
}}
)}

[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5SODimmCrb]
gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
{{
  PCIE_PEG + 1,
  NOT_USED,
  PCIE_PCH + 20,  // PCIE x4 Slot 1
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 6,   // Foxville
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 7,   // M.2_WLAN
  PCIE_PCH,       // M.2_SSD_3
  PCIE_PEG,       // CPU_M.2_SSD
  PCIE_PCH + 12,  // M.2_SSD
  PCIE_PCH + 24,  // TBT
  PCIE_PCH + 8,   // PCIE X4_SLOT_2
  PCIE_PCH + 4,   // PCIE X2_SLOT_3
  NOT_USED,
  NOT_USED
}}
)}


[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr5SODimmErb]
gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
{{
  PCIE_PEG + 1,   // x16 PEG Slot
  NOT_USED,
  PCIE_PCH + 12,  // PCIE x4 Slot 1
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 6,   // Foxville
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 7,   // M.2_WLAN
  PCIE_PCH + 1,   // M.2_WWAN
  PCIE_PEG,       // CPU_M.2 Key M
  PCIE_PCH + 20,  // M.2_SSD 1 Key M
  PCIE_PCH + 24,  // TBT 0
  PCIE_PCH + 8,   // TBT 1
  NOT_USED,
  NOT_USED,
  NOT_USED
}}
)}

[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr4SODimmCrb]
gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
{{
  PCIE_PEG + 1,   // x16 PEG Slot
  NOT_USED,
  PCIE_PCH + 12,  // PCIE x4 Slot 1
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 6,   // Foxville
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 7,   // M.2_WLAN
  PCIE_PCH + 1,   // M.2_WWAN
  PCIE_PEG,       // CPU_M.2 Key M
  PCIE_PCH + 20,  // M.2_SSD 1 Key M
  PCIE_PCH + 24,  // TBT
  NOT_USED,
  NOT_USED,
  NOT_USED,
  NOT_USED
}}
)}

[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr5SODimmAep]
gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
{{
  PCIE_PEG + 1,   // x16 PEG Slot
  NOT_USED,
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 6,   // Foxville
  NOT_USED,
  NOT_USED,
  NOT_USED,
  PCIE_PCH + 24,  // M.2_WLAN
  PCIE_PCH + 1,   // M.2_WWAN
  PCIE_PCH + 20,  // PCH SSD2
  PCIE_PCH + 12,  // PCH SSD1
  PCIE_PCH + 8,   // TBT 0
  NOT_USED,
  NOT_USED,
  NOT_USED,
  NOT_USED
}}
)}