/** @file

;******************************************************************************
;* Copyright (c) 2020 - 2021, Insyde Software Corp. All Rights Reserved.
;*
;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
;* transmit, broadcast, present, recite, release, license or otherwise exploit
;* any part of this publication in any form, by any means, without the prior
;* written permission of Insyde Software Corporation.
;*
;******************************************************************************
*/

#ifndef _NVIDIA_COMMON_ASI_
#define _NVIDIA_COMMON_ASI_

//
// ASL code common define about device
//
#define PCI_SCOPE                             \_SB.PC00
#define IGPU_SCOPE                            PCI_SCOPE.GFX0
#define EC_SCOPE                              PCI_SCOPE.LPCB.H_EC

//
// nVIDIA GPS and Ventura feature usage define
//
#define CPU0_SCOPE                            \_SB.PR00
#define CPU1_SCOPE                            \_SB.PR01
#define CPU2_SCOPE                            \_SB.PR02
#define CPU3_SCOPE                            \_SB.PR03
#define CPU4_SCOPE                            \_SB.PR04
#define CPU5_SCOPE                            \_SB.PR05
#define CPU6_SCOPE                            \_SB.PR06
#define CPU7_SCOPE                            \_SB.PR07
#define CPU8_SCOPE                            \_SB.PR08
#define CPU9_SCOPE                            \_SB.PR09
#define CPU10_SCOPE                           \_SB.PR10
#define CPU11_SCOPE                           \_SB.PR11
#define CPU12_SCOPE                           \_SB.PR12
#define CPU13_SCOPE                           \_SB.PR13
#define CPU14_SCOPE                           \_SB.PR14
#define CPU15_SCOPE                           \_SB.PR15
#define CPU16_SCOPE                           \_SB.PR16
#define CPU17_SCOPE                           \_SB.PR17
#define CPU18_SCOPE                           \_SB.PR18
#define CPU19_SCOPE                           \_SB.PR19
#define CPU20_SCOPE                           \_SB.PR20
#define CPU21_SCOPE                           \_SB.PR21
#define CPU22_SCOPE                           \_SB.PR22
#define CPU23_SCOPE                           \_SB.PR23

//
// nVIDIA return status code
//
#define STATUS_SUCCESS                        0x00000000 // Generic Success
#define STATUS_ERROR_UNSPECIFIED              0x80000001 // Generic unspecified error code
#define STATUS_ERROR_UNSUPPORTED              0x80000002 // Sub-Function not supported

//
// nVIDIA Optimus feature related function define
//
#define NVOP_FUNC_SUPPORT                     0x00
#define NVOP_FUNC_DISPLAYSTATUS               0x05
#define NVOP_FUNC_MDTL                        0x06
#define NVOP_FUNC_GETOBJBYTYPE                0x10
#define NVOP_FUNC_OPTIMUSCAPS                 0x1A
#define NVOP_FUNC_OPTIMUSFLAGS                0x1B

//
// nVIDIA GPS feature related function define
//
#define GPS_FUNC_SUPPORT                      0x00
#define GPS_FUNC_GETCALLBACKS                 0x13
#define GPS_FUNC_PCONTROL                     0x1C
#define GPS_FUNC_PSHARESTATUS                 0x20
#define GPS_FUNC_GETPSS                       0x21
#define GPS_FUNC_SETPPC                       0x22
#define GPS_FUNC_GETPPC                       0x23
#define GPS_FUNC_PSHAREPARAMS                 0x2A

//
// nVIDIA GC6 feature related function define
//
#define JT_REVISION_ID                        0x00000100
#define JT_FUNC_SUPPORT                       0x00000000
#define JT_FUNC_CAPS                          0x00000001
#define JT_FUNC_POLICYSELECT                  0x00000002
#define JT_FUNC_POWERCONTROL                  0x00000003
#define JT_FUNC_PLATPOLICY                    0x00000004
#define JT_FUNC_DISPLAYSTATUS                 0x00000005
#define JT_FUNC_MDTL                          0x00000006

//
// nVIDIA NBCI feature related function define
//
#define NBCI_FUNC_SUPPORT                     0x00
#define NBCI_FUNC_GETOBJBYTYPE                0x10
#define NBCI_FUNC_GETBACKLIGHT                0x14
#define NBCI_FUNC_GETLICENSE                  0x16

//
// nVIDIA PCF feature related function define
//
#define NVPCF_FUNC_GET_SUPPORTED                     0x00
#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES          0x01
#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS             0x02
#define NVPCF_FUNC_GET_WM2_TBAND_TABLES              0x03
#define NVPCF_FUNC_GET_WM2_SL_MAP_TABLES             0x04
#define NVPCF_FUNC_GET_WM2_DYNAMIC_PARAMS            0x05
#define NVPCF_FUNC_CPU_CONTROL                       0x06
#define NVPCF_FUNC_GPU_INFO                          0x07
#define NVPCF_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE  0x08
#define NVPCF_FUNC_CPU_TDP_CONTROL                   0x09

//
// MXM Function define
//
#define MXM_FUNC_MXSS                         0x00
#define MXM_FUNC_MXDP                         0x05
#define MXM_FUNC_MDTL                         0x06
#define MXM_FUNC_MXMS                         0x10
#define MXM_FUNC_MXMI                         0x18
#define MXM_FUNC_MXCB                         0x19

#endif