/**@file @copyright INTEL CONFIDENTIAL Copyright (c) 2015 - 2017 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement. @par Specification Reference: **/ // // Definition for MSPDRTREQ bits, which are used for ASL code to // trigger requests for ModPHY SPD gating. // #ifndef _HSIO_DEFINE_ASL_ #define _HSIO_DEFINE_ASL_ #define MODPHY_SPD_GATING_PCIE_RP1 0 #define MODPHY_SPD_GATING_PCIE_RP2 1 #define MODPHY_SPD_GATING_PCIE_RP3 2 #define MODPHY_SPD_GATING_PCIE_RP4 3 #define MODPHY_SPD_GATING_PCIE_RP5 4 #define MODPHY_SPD_GATING_PCIE_RP6 5 #define MODPHY_SPD_GATING_PCIE_RP7 6 #define MODPHY_SPD_GATING_PCIE_RP8 7 #define MODPHY_SPD_GATING_PCIE_RP9 8 #define MODPHY_SPD_GATING_PCIE_RP10 9 #define MODPHY_SPD_GATING_PCIE_RP11 10 #define MODPHY_SPD_GATING_PCIE_RP12 11 #define MODPHY_SPD_GATING_PCIE_RP13 12 #define MODPHY_SPD_GATING_PCIE_RP14 13 #define MODPHY_SPD_GATING_PCIE_RP15 14 #define MODPHY_SPD_GATING_PCIE_RP16 15 #define MODPHY_SPD_GATING_PCIE_RP17 16 #define MODPHY_SPD_GATING_PCIE_RP18 17 #define MODPHY_SPD_GATING_PCIE_RP19 18 #define MODPHY_SPD_GATING_PCIE_RP20 19 #define MODPHY_SPD_GATING_SATA 20 #define MODPHY_SPD_GATING_GBE 21 #define MODPHY_SPD_GATING_XHCI 22 #define MODPHY_SPD_GATING_XDCI 23 #define MODPHY_SPD_GATING_UFS 24 #endif // _HSIO_DEFINE_ASL_