/** @file
  PCH SMM private lib.

@copyright
  INTEL CONFIDENTIAL
  Copyright 2018 - 2020 Intel Corporation.

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  source code ("Material") are owned by Intel Corporation or its suppliers or
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  confidential information of Intel Corporation and its suppliers and licensors,
  and is protected by worldwide copyright and trade secret laws and treaty
  provisions. No part of the Material may be used, copied, reproduced, modified,
  published, uploaded, posted, transmitted, distributed, or disclosed in any way
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  Unless otherwise agreed by Intel in writing, you may not remove or alter
  this notice or any other notice embedded in Materials by Intel or
  Intel's suppliers or licensors in any way.

  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
  the terms of your license agreement with Intel or your vendor. This file may
  be modified by the user, subject to additional terms of the license agreement.

@par Specification Reference:
**/

#include <Uefi/UefiBaseType.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Library/CpuPlatformLib.h>
#include <CpuRegs.h>
#include <Register/CommonMsr.h>
#include <Register/PttPtpRegs.h>

STATIC UINT32 mBiosGuardEnabled = ~0u;

/**
  Set InSmm.Sts bit
**/
VOID
PchSetInSmmSts (
  VOID
  )
{
  UINT32      Data32;

  //
  // When BIOS GUARD is enabled, the MSR 1FEh is invalid.
  //
  if (mBiosGuardEnabled != 0) {
    if (mBiosGuardEnabled == 1) {
      return;
    }
    mBiosGuardEnabled = IsBiosGuardEnabled () ? 1 : 0;
    if (mBiosGuardEnabled == 1) {
      return;
    }
  }

  ///
  /// If platform disables TXT_PTLEN strap, NL socket(s) will target abort
  /// when trying to access LT register space below, and writes to
  /// NL's MSR 0x1FE will GP fault. Check straps enabled first.
  ///

  Data32 = MmioRead32 (R_LT_EXISTS);

  if (Data32 == 0xFFFFFFFF) {
    return;
  }
  ///
  /// Read memory location FED30880h OR with 00000001h, place the result in EAX,
  /// and write data to lower 32 bits of MSR 1FEh (sample code available)
  ///
  Data32 = MmioRead32 (R_LT_UCS);
  AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 | BIT0);
  ///
  /// Read FED30880h back to ensure the setting went through.
  ///
  Data32 = MmioRead32 (R_LT_UCS);
}

/**
  Clear InSmm.Sts bit
**/
VOID
PchClearInSmmSts (
  VOID
  )
{
  UINT32      Data32;

  //
  // When BIOS GUARD is enabled, the MSR 1FEh is invalid.
  //
  if (mBiosGuardEnabled != 0) {
    if (mBiosGuardEnabled == 1) {
      return;
    }
    mBiosGuardEnabled = IsBiosGuardEnabled () ? 1 : 0;
    if (mBiosGuardEnabled == 1) {
      return;
    }
  }

  ///
  /// If platform disables TXT_PTLEN strap, NL socket(s) will target abort
  /// when trying to access LT register space below, and writes to
  /// NL's MSR 0x1FE will GP fault. Check straps enabled first.
  ///

  Data32 = MmioRead32 (R_LT_EXISTS);
  if (Data32 == 0xFFFFFFFF) {
    return;
  }

  ///
  /// Read memory location FED30880h AND with FFFFFFFEh, place the result in EAX,
  /// and write data to lower 32 bits of MSR 1FEh (sample code available)
  ///
  Data32 = MmioRead32 (R_LT_UCS);
  AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 & (UINT32) (~BIT0));
  ///
  /// Read FED30880h back to ensure the setting went through.
  ///
  Data32 = MmioRead32 (R_LT_UCS);
}