//
// Automatically generated by GenNvs ver 2.4.6
// Please DO NOT modify !!!
//
/**@file
@copyright
INTEL CONFIDENTIAL
Copyright 2016 - 2021 Intel Corporation.
The source code contained or described herein and all documents related to the
source code ("Material") are owned by Intel Corporation or its suppliers or
licensors. Title to the Material remains with Intel Corporation or its suppliers
and licensors. The Material may contain trade secrets and proprietary and
confidential information of Intel Corporation and its suppliers and licensors,
and is protected by worldwide copyright and trade secret laws and treaty
provisions. No part of the Material may be used, copied, reproduced, modified,
published, uploaded, posted, transmitted, distributed, or disclosed in any way
without Intel's prior express written permission.
No license under any patent, copyright, trade secret or other intellectual
property right is granted to or conferred upon you by disclosure or delivery
of the Materials, either expressly, by implication, inducement, estoppel or
otherwise. Any license under such intellectual property rights must be
express and approved by Intel in writing.
Unless otherwise agreed by Intel in writing, you may not remove or alter
this notice or any other notice embedded in Materials by Intel or
Intel's suppliers or licensors in any way.
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
the terms of your license agreement with Intel or your vendor. This file may
be modified by the user, subject to additional terms of the license agreement.
@par Specification Reference:
**/
//
// Define SA NVS Area operation region.
//
OperationRegion(SANV,SystemMemory,SANB,SANL)
Field(SANV,AnyAcc,Lock,Preserve)
{ Offset(0), ASLB, 32, // Offset(0), IGD OpRegion base address
Offset(4), IMON, 8, // Offset(4), IMON Current Value
Offset(5), IGDS, 8, // Offset(5), IGD State (Primary Display = 1)
Offset(6), IBTT, 8, // Offset(6), IGD Boot Display Device
Offset(7), IPAT, 8, // Offset(7), IGD Panel Type CMOS option
Offset(8), IPSC, 8, // Offset(8), IGD Panel Scaling
Offset(9), IBIA, 8, // Offset(9), IGD BIA Configuration
Offset(10), ISSC, 8, // Offset(10), IGD SSC Configuration
Offset(11), IF1E, 8, // Offset(11), IGD Function 1 Enable
Offset(12), HVCO, 8, // Offset(12), HPLL VCO
Offset(13), GSMI, 8, // Offset(13), GMCH SMI/SCI mode (0=SCI)
Offset(14), PAVP, 8, // Offset(14), IGD PAVP data
Offset(15), CADL, 8, // Offset(15), Current Attached Device List
Offset(16), CSTE, 16, // Offset(16), Current Display State
Offset(18), NSTE, 16, // Offset(18), Next Display State
Offset(20), NDID, 8, // Offset(20), Number of Valid Device IDs
Offset(21), DID1, 32, // Offset(21), Device ID 1
Offset(25), DID2, 32, // Offset(25), Device ID 2
Offset(29), DID3, 32, // Offset(29), Device ID 3
Offset(33), DID4, 32, // Offset(33), Device ID 4
Offset(37), DID5, 32, // Offset(37), Device ID 5
Offset(41), DID6, 32, // Offset(41), Device ID 6
Offset(45), DID7, 32, // Offset(45), Device ID 7
Offset(49), DID8, 32, // Offset(49), Device ID 8
Offset(53), DID9, 32, // Offset(53), Device ID 9
Offset(57), DIDA, 32, // Offset(57), Device ID 10
Offset(61), DIDB, 32, // Offset(61), Device ID 11
Offset(65), DIDC, 32, // Offset(65), Device ID 12
Offset(69), DIDD, 32, // Offset(69), Device ID 13
Offset(73), DIDE, 32, // Offset(73), Device ID 14
Offset(77), DIDF, 32, // Offset(77), Device ID 15
Offset(81), DIDX, 32, // Offset(81), Device ID for eDP device
Offset(85), NXD1, 32, // Offset(85), Next state DID1 for _DGS
Offset(89), NXD2, 32, // Offset(89), Next state DID2 for _DGS
Offset(93), NXD3, 32, // Offset(93), Next state DID3 for _DGS
Offset(97), NXD4, 32, // Offset(97), Next state DID4 for _DGS
Offset(101), NXD5, 32, // Offset(101), Next state DID5 for _DGS
Offset(105), NXD6, 32, // Offset(105), Next state DID6 for _DGS
Offset(109), NXD7, 32, // Offset(109), Next state DID7 for _DGS
Offset(113), NXD8, 32, // Offset(113), Next state DID8 for _DGS
Offset(117), NXDX, 32, // Offset(117), Next state DID for eDP
Offset(121), LIDS, 8, // Offset(121), Lid State (Lid Open = 1)
Offset(122), KSV0, 32, // Offset(122), First four bytes of AKSV (manufacturing mode)
Offset(126), KSV1, 8, // Offset(126), Fifth byte of AKSV (manufacturing mode)
Offset(127), BRTL, 8, // Offset(127), Brightness Level Percentage
Offset(128), ALSE, 8, // Offset(128), Ambient Light Sensor Enable
Offset(129), ALAF, 8, // Offset(129), Ambient Light Adjusment Factor
Offset(130), LLOW, 8, // Offset(130), LUX Low Value
Offset(131), LHIH, 8, // Offset(131), LUX High Value
Offset(132), ALFP, 8, // Offset(132), Active LFP
Offset(133), IPTP, 8, // Offset(133), IPU ACPI device type (0=Disabled, 1=AVStream virtual device as child of GFX)
Offset(134), EDPV, 8, // Offset(134), Check for eDP display device
Offset(135), HGMD, 8, // Offset(135), SG Mode (0=Disabled, 1=HG Muxed, 2=HG Muxless, 3=DGPU Only)
Offset(136), HGFL, 8, // Offset(136), HG Feature List
Offset(137), SGGP, 8, // Offset(137), PCIe0 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
Offset(138), HRE0, 8, // Offset(138), PCIe0 HLD RST IO Expander Number
Offset(139), HRG0, 32, // Offset(139), PCIe0 HLD RST GPIO Number
Offset(143), HRA0, 8, // Offset(143), PCIe0 HLD RST GPIO Active Information
Offset(144), PWE0, 8, // Offset(144), PCIe0 PWR Enable IO Expander Number
Offset(145), PWG0, 32, // Offset(145), PCIe0 PWR Enable GPIO Number
Offset(149), PWA0, 8, // Offset(149), PCIe0 PWR Enable GPIO Active Information
Offset(150), P1GP, 8, // Offset(150), PCIe1 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
Offset(151), HRE1, 8, // Offset(151), PCIe1 HLD RST IO Expander Number
Offset(152), HRG1, 32, // Offset(152), PCIe1 HLD RST GPIO Number
Offset(156), HRA1, 8, // Offset(156), PCIe1 HLD RST GPIO Active Information
Offset(157), PWE1, 8, // Offset(157), PCIe1 PWR Enable IO Expander Number
Offset(158), PWG1, 32, // Offset(158), PCIe1 PWR Enable GPIO Number
Offset(162), PWA1, 8, // Offset(162), PCIe1 PWR Enable GPIO Active Information
Offset(163), P2GP, 8, // Offset(163), PCIe2 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
Offset(164), HRE2, 8, // Offset(164), PCIe2 HLD RST IO Expander Number
Offset(165), HRG2, 32, // Offset(165), PCIe2 HLD RST GPIO Number
Offset(169), HRA2, 8, // Offset(169), PCIe2 HLD RST GPIO Active Information
Offset(170), PWE2, 8, // Offset(170), PCIe2 PWR Enable IO Expander Number
Offset(171), PWG2, 32, // Offset(171), PCIe2 PWR Enable GPIO Number
Offset(175), PWA2, 8, // Offset(175), PCIe2 PWR Enable GPIO Active Information
Offset(176), P3GP, 8, // Offset(176), PCIe3 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
Offset(177), HRE3, 8, // Offset(177), PCIe3 HLD RST IO Expander Number
Offset(178), HRG3, 32, // Offset(178), PCIe3 HLD RST GPIO Number
Offset(182), HRA3, 8, // Offset(182), PCIe3 HLD RST GPIO Active Information
Offset(183), PWE3, 8, // Offset(183), PCIe3 PWR Enable IO Expander Number
Offset(184), PWG3, 32, // Offset(184), PCIe3 PWR Enable GPIO Number
Offset(188), PWA3, 8, // Offset(188), PCIe3 PWR Enable GPIO Active Information
Offset(189), P3WK, 32, // Offset(189), PCIe3 RTD3 Device Wake GPIO Number
Offset(193), DLPW, 16, // Offset(193), Delay after power enable for PCIe
Offset(195), DLHR, 16, // Offset(195), Delay after Hold Reset for PCIe
Offset(197), EECP, 8, // Offset(197), PCIe0 Endpoint Capability Structure Offset
Offset(198), XBAS, 32, // Offset(198), Any Device's PCIe Config Space Base Address
Offset(202), GBAS, 16, // Offset(202), GPIO Base Address
Offset(204), NVGA, 32, // Offset(204), NVIG opregion address
Offset(208), NVHA, 32, // Offset(208), NVHM opregion address
Offset(212), AMDA, 32, // Offset(212), AMDA opregion address
Offset(216), LTRX, 8, // Offset(216), Latency Tolerance Reporting Enable
Offset(217), OBFX, 8, // Offset(217), Optimized Buffer Flush and Fill
Offset(218), LTRY, 8, // Offset(218), Latency Tolerance Reporting Enable
Offset(219), OBFY, 8, // Offset(219), Optimized Buffer Flush and Fill
Offset(220), LTRZ, 8, // Offset(220), Latency Tolerance Reporting Enable
Offset(221), OBFZ, 8, // Offset(221), Optimized Buffer Flush and Fill
Offset(222), LTRW, 8, // Offset(222), Latency Tolerance Reporting Enable
Offset(223), OBFA, 8, // Offset(223), Optimized Buffer Flush and Fill
Offset(224), SMSL, 16, // Offset(224), SA Peg Latency Tolerance Reporting Max Snoop Latency
Offset(226), SNSL, 16, // Offset(226), SA Peg Latency Tolerance Reporting Max No Snoop Latency
Offset(228), M64B, 64, // Offset(228), Base of above 4GB MMIO resource
Offset(236), M64L, 64, // Offset(236), Length of above 4GB MMIO resource
Offset(244), CPEX, 32, // Offset(244), CPU ID info to get Family Id or Stepping
Offset(248), M32B, 32, // Offset(248), Base of below 4GB MMIO resource
Offset(252), M32L, 32, // Offset(252), Length of below 4GB MMIO resource
Offset(256), P0WK, 32, // Offset(256), PCIe0 RTD3 Device Wake GPIO Number
Offset(260), P1WK, 32, // Offset(260), PCIe1 RTD3 Device Wake GPIO Number
Offset(264), P2WK, 32, // Offset(264), PCIe2 RTD3 Device Wake GPIO Number
Offset(268), VTDS, 8, // Offset(268), VT-d Enable/Disable
Offset(269), VTB1, 32, // Offset(269), VT-d Base Address 1
Offset(273), VTB2, 32, // Offset(273), VT-d Base Address 2
Offset(277), VTB3, 32, // Offset(277), VT-d Base Address 3
Offset(281), VTB4, 32, // Offset(281), VT-d Base Address 4 (iTBT PCIE0)
Offset(285), VTB5, 32, // Offset(285), VT-d Base Address 5 (iTBT PCIE1)
Offset(289), VTB6, 32, // Offset(289), VT-d Base Address 6 (iTBT PCIE2)
Offset(293), VTB7, 32, // Offset(293), VT-d Base Address 7 (iTBT PCIE3)
Offset(297), VE1V, 16, // Offset(297), VT-d Engine#1 Vendor ID
Offset(299), VE2V, 16, // Offset(299), VT-d Engine#2 Vendor ID
Offset(301), RPIN, 8, // Offset(301), RootPort Number
Offset(302), RPBA, 32, // Offset(302), RootPortAddress
Offset(306), CTHM, 8, // Offset(306), CPU Trace Hub Mode
Offset(307), SIME, 8, // Offset(307), Simics Environment information
Offset(308), THCE, 8, // Offset(308), TCSS XHCI Device Enable
Offset(309), TDCE, 8, // Offset(309), TCSS XDCI Device Enable
Offset(310), DME0, 8, // Offset(310), TCSS DMA 0 Device Enable
Offset(311), DME1, 8, // Offset(311), TCSS DMA 1 Device Enable
Offset(312), TRE0, 8, // Offset(312), TCSS ItbtPcieRp PCIE RP 0 Device Enable
Offset(313), TRE1, 8, // Offset(313), TCSS ItbtPcieRp PCIE RP 1 Device Enable
Offset(314), TRE2, 8, // Offset(314), TCSS ItbtPcieRp PCIE RP 2 Device Enable
Offset(315), TRE3, 8, // Offset(315), TCSS ItbtPcieRp PCIE RP 3 Device Enable
Offset(316), TPA0, 32, // Offset(316), TCSS ItbtPcie Root Port address 0
Offset(320), TPA1, 32, // Offset(320), TCSS ItbtPcie Root Port address 1
Offset(324), TPA2, 32, // Offset(324), TCSS ItbtPcie Root Port address 2
Offset(328), TPA3, 32, // Offset(328), TCSS ItbtPcie Root Port address 3
Offset(332), TCDS, 32, // Offset(332), TCSS xDCI Power Down Scale Value, DWC_USB3_GCTL_INIT[31:19]
Offset(336), TCIT, 8, // Offset(336), TCSS xDCI Int Pin
Offset(337), TCIR, 8, // Offset(337), TCSS xDCI Irq Number
Offset(338), TRTD, 8, // Offset(338), TCSS RTD3
Offset(339), ITM0, 32, // Offset(339), TCSS DMA0 RMRR address
Offset(343), ITM1, 32, // Offset(343), TCSS DMA1 RMRR address
Offset(347), LTE0, 8, // Offset(347), Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
Offset(348), LTE1, 8, // Offset(348), Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
Offset(349), LTE2, 8, // Offset(349), Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
Offset(350), LTE3, 8, // Offset(350), Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
Offset(351), PSL0, 16, // Offset(351), PCIE LTR max snoop Latency 0
Offset(353), PSL1, 16, // Offset(353), PCIE LTR max snoop Latency 1
Offset(355), PSL2, 16, // Offset(355), PCIE LTR max snoop Latency 2
Offset(357), PSL3, 16, // Offset(357), PCIE LTR max snoop Latency 3
Offset(359), PNS0, 16, // Offset(359), PCIE LTR max no snoop Latency 0
Offset(361), PNS1, 16, // Offset(361), PCIE LTR max no snoop Latency 1
Offset(363), PNS2, 16, // Offset(363), PCIE LTR max no snoop Latency 2
Offset(365), PNS3, 16, // Offset(365), PCIE LTR max no snoop Latency 3
Offset(367), IMRY, 8, // Offset(367), IOM Ready
Offset(368), TIVS, 8, // Offset(368), TCSS IOM VccSt
Offset(369), PG0E, 8, // Offset(369), <0:Disabled, 1:Enabled>
Offset(370), PG1E, 8, // Offset(370), <0:Disabled, 1:Enabled>
Offset(371), PG2E, 8, // Offset(371), <0:Disabled, 1:Enabled>
Offset(372), PG3E, 8, // Offset(372), <0:Disabled, 1:Enabled>
Offset(373), VMDE, 8, // Offset(373), VMD Device Enable
Offset(374), DIDY, 32, // Offset(374), Device ID for second LFP device
Offset(378), NXDY, 32, // Offset(378), Next state DID for Second Display
Offset(382), SLTS, 8, // Offset(382), PCIe slot selection
Offset(383), VMR1, 8, // Offset(383), VMD PCH RP 1 to 8 mapped under VMD
Offset(384), VMR2, 8, // Offset(384), VMD PCH RP 9 to 16 mapped under VMD
Offset(385), VMR3, 8, // Offset(385), VMD PCH RP 17 to 24 mapped under VMD
Offset(386), VMR4, 8, // Offset(386), VMD PCH RP 25 to 32 mapped under VMD
Offset(387), VMS0, 8, // Offset(387), VMD SATA PORT 0 to 7 mapped under VMD
Offset(388), VMCP, 8, // Offset(388), VMD CPU RP mapped under VMD
Offset(389), CPRT, 8, // Offset(389), RTD3 Support for CPU PCIE.
Offset(390), CSLU, 32, // Offset(390), Lane Used of each CSI Port <0:Not Configured, 1:x1, 2:x2, 3:x3 4:x4>
Offset(394), CSSP, 32, // Offset(394), Speed of each CSI Port <0:Not configured, 1:<416GMbps, 2:<1.5Gbps, 3:<2.0Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps>
Offset(398), MPGN, 8, // Offset(398), Max PEG port number
Offset(399), CMBM, 8, // Offset(399), Current Memory Boot Mode <0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION>
Offset(400), DPMS, 8, // Offset(400), Dynamic PMem Support <0: Disabled, 1:Enabled>
Offset(401), PMSA, 64, // Offset(401), Private Pmem Starting address
Offset(409), PMRL, 64, // Offset(409), Private Pmem Range Length
Offset(417), PBR1, 8, // Offset(417), Is bridge device behind Peg1
Offset(418), PBR2, 8, // Offset(418), Is bridge device behind Peg2
Offset(419), PBR3, 8, // Offset(419), Is bridge device behind Peg3
Offset(420), PPA0, 32, // Offset(420), CpuPcieRp Address 1
Offset(424), PPA1, 32, // Offset(424), CpuPcieRp address 2
Offset(428), PPA2, 32, // Offset(428), CpuPcieRp address 3
Offset(432), PPA3, 32, // Offset(432), CpuPcieRp Address 4
Offset(436), REGO, 16, // Offset(436), MCH RegBar Offset
}