214 lines
8.2 KiB
C
214 lines
8.2 KiB
C
/** @file
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;******************************************************************************
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;* Copyright (c) 2012 - 2019, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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/*++
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Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
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This software and associated documentation (if any) is furnished
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under a license and may only be used or copied in accordance
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with the terms of the license. Except as permitted by such
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license, no part of this software or documentation may be
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reproduced, stored in a retrieval system, or transmitted in any
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form or by any means without the express written consent of
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Intel Corporation.
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Module Name:
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PlatformMemoryRange.h
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Abstract:
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Platform Memory Range PPI as defined in EFI 2.0
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PPI for reserving special purpose memory ranges.
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--*/
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#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_
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#define _PEI_PLATFORM_MEMORY_RANGE_H_
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#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \
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{ \
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0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \
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}
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typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI PEI_PLATFORM_MEMORY_RANGE_PPI;
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#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
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#define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF
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#define PEI_MR_OPTION_ROM_NONE 0x00000000
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#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001
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#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002
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#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004
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#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008
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#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010
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#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020
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#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040
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#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080
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#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100
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#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200
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#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400
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#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800
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#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000
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#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000
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#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000
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#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000
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//
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// SMRAM Memory Range
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//
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#define PEI_MEMORY_RANGE_SMRAM UINT32
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#define PEI_MR_SMRAM_ALL 0xFFFFFFFF
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#define PEI_MR_SMRAM_NONE 0x00000000
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#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
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#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
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#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
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#define PEI_MR_SMRAM_HSEG_MASK 0x00020000
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#define PEI_MR_SMRAM_TSEG_MASK 0x00040000
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//
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// If adding additional entries, SMRAM Size
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// is a multiple of 128KB.
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//
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#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
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#define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001
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#define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002
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#define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004
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#define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008
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#define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010
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#define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020
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#define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040
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#define PEI_MR_SMRAM_SIZE_16384K_MASK 0x00000080
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#define PEI_MR_SMRAM_SIZE_32768K_MASK 0x00000100
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#define PEI_MR_SMRAM_SIZE_65536K_MASK 0x00000200
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#define PEI_MR_SMRAM_SIZE_131072K_MASK 0x00000400
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#define PEI_MR_SMRAM_SIZE_1M_MASK PEI_MR_SMRAM_SIZE_1024K_MASK
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#define PEI_MR_SMRAM_SIZE_2M_MASK PEI_MR_SMRAM_SIZE_2048K_MASK
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#define PEI_MR_SMRAM_SIZE_4M_MASK PEI_MR_SMRAM_SIZE_4096K_MASK
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#define PEI_MR_SMRAM_SIZE_8M_MASK PEI_MR_SMRAM_SIZE_8192K_MASK
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#define PEI_MR_SMRAM_SIZE_16M_MASK PEI_MR_SMRAM_SIZE_16384K_MASK
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#define PEI_MR_SMRAM_SIZE_32M_MASK PEI_MR_SMRAM_SIZE_32768K_MASK
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#define PEI_MR_SMRAM_SIZE_64M_MASK PEI_MR_SMRAM_SIZE_65536K_MASK
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#define PEI_MR_SMRAM_SIZE_128M_MASK PEI_MR_SMRAM_SIZE_131072K_MASK
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#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001
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#define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001
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#define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001
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#define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001
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#define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001
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#define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002
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#define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002
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#define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004
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#define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004
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#define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008
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#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008
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#define PEI_MR_SMRAM_TSEG_2048K_CACHE 0x80040010
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#define PEI_MR_SMRAM_TSEG_2048K_NOCACHE 0x00040010
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#define PEI_MR_SMRAM_TSEG_4096K_CACHE 0x80040020
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#define PEI_MR_SMRAM_TSEG_4096K_NOCACHE 0x00040020
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#define PEI_MR_SMRAM_TSEG_8192K_CACHE 0x80040040
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#define PEI_MR_SMRAM_TSEG_8192K_NOCACHE 0x00040040
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//
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// Graphics Memory Range
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//
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#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32
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#define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF
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#define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000
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#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000
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//
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// If adding additional entries, PCI Memory Size
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// is a multiple of 512KB.
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//
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#define PEI_MR_PCI_MEMORY_NONE 0x00000000
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#define PEI_MR_PCI_MEMORY_SIZE_MASK 0x0000FFFF
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#define PEI_MR_PCI_MEMORY_4M 0x00000008
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#define PEI_MR_PCI_MEMORY_5M 0x0000000A
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#define PEI_MR_PCI_MEMORY_8M 0x00000010
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#define PEI_MR_PCI_MEMORY_16M 0x00000020
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#define PEI_MR_PCI_MEMORY_32M 0x00000040
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//
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// If adding additional entries, Graphics Memory Size
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// is a multiple of 512KB.
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//
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#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF
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#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001
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#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001
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#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002
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#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002
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#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008
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#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008
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#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010
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#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010
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#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020
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#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020
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#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040
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#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040
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#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060
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#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060
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#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080
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#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080
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#define PEI_MR_GRAPHICS_MEMORY_96M_NOCACHE 0x000000C0
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#define PEI_MR_GRAPHICS_MEMORY_96M_CACHE 0x800000C0
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#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100
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#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100
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#define PEI_MR_GRAPHICS_MEMORY_160M_NOCACHE 0x00000140
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#define PEI_MR_GRAPHICS_MEMORY_160M_CACHE 0x80000140
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#define PEI_MR_GRAPHICS_MEMORY_224M_NOCACHE 0x000001C0
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#define PEI_MR_GRAPHICS_MEMORY_224M_CACHE 0x800001C0
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#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200
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#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200
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#define PEI_MR_GRAPHICS_MEMORY_352M_NOCACHE 0x000002C0
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#define PEI_MR_GRAPHICS_MEMORY_352M_CACHE 0x800002C0
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#define PEI_MR_GRAPHICS_MEMORY_512M_NOCACHE 0x00000400
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#define PEI_MR_GRAPHICS_MEMORY_512M_CACHE 0x80000400
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#define PEI_MR_GRAPHICS_MEMORY_1024M_NOCACHE 0x00000800
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#define PEI_MR_GRAPHICS_MEMORY_1024M_CACHE 0x80000800
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#define PEI_MR_GRAPHICS_MEMORY_2048M_NOCACHE 0x00001000
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#define PEI_MR_GRAPHICS_MEMORY_2048M_CACHE 0x80001000
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#define PEI_GGMS_2M_NOCACHE 0x00000004
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#define PEI_GGMS_2M_CACHE 0x80000004
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#define PEI_GGMS_4M_NOCACHE 0x00000008
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#define PEI_GGMS_4M_CACHE 0x80000008
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//
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// Pci Memory Hole
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//
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#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
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#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001
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typedef
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EFI_STATUS
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(EFIAPI *PEI_CHOOSE_RANGES) (
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_PLATFORM_MEMORY_RANGE_PPI * This,
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IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask,
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IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask,
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IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask,
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IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask
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);
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struct _PEI_PLATFORM_MEMORY_RANGE_PPI {
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PEI_CHOOSE_RANGES ChooseRanges;
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};
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extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;
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#endif
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