841 lines
26 KiB
Plaintext
841 lines
26 KiB
Plaintext
/** @file
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;******************************************************************************
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;* Copyright (c) 2021, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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/** @file
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PCIe Root Port Generic PCIE Device Rtd3 file.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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/// @details
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/// Code in this file uses following variables:
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/// SCLK: ICC Clock number - optional
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/// WAKG: WAKE GPIO pad - optional
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/// Below objects should be defined according to the format described in PinDriverLib.asl
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/// RSTG: reset pin definition - mandatory
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/// PWRG: power GPIO pad - optional
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/// WAKP: Flag to indicate that power gating must not be performed if WAKE is enabled - optional
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/** @defgroup pcie_scope PCIe Root Port Scope **/
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//
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// AcpiPinDriverLib imports(from DSDT in platform)
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//
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External (\PIN.STA, MethodObj)
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External (\PIN.ON, MethodObj)
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External (\PIN.OFF, MethodObj)
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//
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// GpioLib imports(DSDT)
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//
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External (\_SB.SHPO, MethodObj)
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//
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// HSIO lib imports
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//
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External (\_SB.PSD0, MethodObj)
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External (\_SB.PSD3, MethodObj)
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External (DVES, MethodObj)
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External (DHDW, MethodObj)
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External (EHDW, MethodObj)
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External (D3HT, FieldUnitObj) // CPU PCIE RP Power State
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External (PCPB, IntObj) // PCIe core power veto bitmask, default 0 - allow for core power removal
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External (HBSL, FieldUnitObj)
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External (\HBCL, FieldUnitObj)
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External (\HBPL, FieldUnitObj)
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External (TMCS, IntObj)
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External (CEMP, MethodObj)
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//[-start-210816-IB05660174-add]//
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External (\DGPV)
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#if FeaturePcdGet (PcdHybridGraphicsSupported)
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#define PCI_SCOPE \_SB.PC00
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//[-start-210917-GEORGE0004-modify]//
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//[-start-210918-QINGLIN0068-modify]//
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//#ifdef S77014_SUPPORT
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#if defined(S77014_SUPPORT) || defined(S570_SUPPORT) || defined(S77014IAH_SUPPORT)
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//[-end-210918-QINGLIN0068-modify]//
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#define DGPU_BRIDGE_SCOPE PCI_SCOPE.PEG2
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#else
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#define DGPU_BRIDGE_SCOPE PCI_SCOPE.PEG1
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#endif
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//[-end-210917-GEORGE0004-modify]//
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#define DGPU_DEVICE PEGP
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#define DGPU_SCOPE DGPU_BRIDGE_SCOPE.DGPU_DEVICE
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#define NVIDIA_VID 0x10DE
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#define NV_GEN_17 17
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#define NV_GEN_20 20
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External (DGPU_BRIDGE_SCOPE.CEDR, FieldUnitObj)
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External (DGPU_BRIDGE_SCOPE.CMDR, FieldUnitObj)
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External (DGPU_BRIDGE_SCOPE.D0ST, FieldUnitObj)
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External (DGPU_BRIDGE_SCOPE.GSTA, MethodObj)
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External (DGPU_BRIDGE_SCOPE.LREN, FieldUnitObj)
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External (DGPU_SCOPE.HDAE, FieldUnitObj)
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External (DGPU_SCOPE.LTRE, IntObj)
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External (DGPU_SCOPE.NVID, FieldUnitObj)
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External (DGPU_SCOPE.PWGD, FieldUnitObj)
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External (DGPU_SCOPE.SSSV, FieldUnitObj)
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External (PCI_SCOPE.DGCX, IntObj)
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External (PCI_SCOPE.DSSV, FieldUnitObj)
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External (PCI_SCOPE.NVGE, FieldUnitObj)
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External (PCI_SCOPE.GC6I, MethodObj)
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External (PCI_SCOPE.GC6O, MethodObj)
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External (PCI_SCOPE.NINI, MethodObj)
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External (PCI_SCOPE.OPTF, FieldUnitObj)
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External (PCI_SCOPE.TDGC, IntObj)
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External (PCI_SCOPE.TGPC, BuffObj)
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//External (\DLHR)
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//External (\DLPW)
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#endif
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//[-end-210816-IB05660174-add]//
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//[-start-210915-QINGLIN0068-add]//
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#if defined(C770_SUPPORT) || defined(S370_SUPPORT) || defined(S570_SUPPORT) || defined(S77014_SUPPORT) || defined(S77014IAH_SUPPORT)
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External (\_SB.PC00.LPCB.EC0.ECAV)
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External (\_SB.PC00.LPCB.EC0.LfcM)
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External (\_SB.PC00.LPCB.EC0.GATY)
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#endif
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//[-end-210915-QINGLIN0068-add]//
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// WAKE enable on PCIe device.
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Name (WKEN, 0)
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// Last OFF Timestamp (WOFF): The time stamp of the last power resource _OFF method evaluation
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Name (WOFF, 0)
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Name (LNRD, 0) // Delay before PERST# assertion in us
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//
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// The deepest D-state supported by this device in the S0 system sleeping state where the device can wake itself,
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// "4" represents D3cold.
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//
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Method (_S0W, 0x0, NotSerialized)
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{
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If (CondRefOf (RD3C)) {
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If (LEqual (RD3C, 0x02)) {
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Return (0x4)
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}
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}
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//[-start-210816-IB05660174-modify]//
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//[-start-211125-IB05660187-modify]//
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#if FeaturePcdGet (PcdHybridGraphicsSupported)
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Return (0x4)
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#else
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Return (0x0)
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#endif
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//[-end-211125-IB05660187-modify]//
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//[-end-210816-IB05660174-modify]//
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}
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//
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// Device Sleep Wake - sets the sleep and wake transition states for a device.
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// ACPI Specification Defined Method. Called by OSPM.
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//
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Method (_DSW, 3, NotSerialized)
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{
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/// This method is used to enable/disable wake from PCIe (WKEN)
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If (Arg1)
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{ /// If entering Sx, enable Sx WAKE
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Store (1, WKEN)
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} Else { /// If Staying in S0
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If (LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake
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{ ///- Set PME
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Store (1, WKEN)
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} Else { ///- Disable runtime PME, either because staying in D0 or disabling wake
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Store (0, WKEN)
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}
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}
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/** @defgroup pcie_dsw PCIE _DSW **/
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} // End _DSW
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Method (PPS0, 0, Serialized) { // Platform specific PCIe root port _PS0 Hook Function.
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}
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Method (PPS3, 0, Serialized) { // Platform specific PCIe root port _PS3 Hook Function.
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}
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//
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// PCIe slot power resource definition
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//
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PowerResource (PXP, 0, 0) {
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Method (_STA, 0) {
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//
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// Check if PCIE RP is available or Not by Checking Vendor and Device ID.
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//
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If (LEqual (VDID, 0xFFFFFFFF)) {
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Return (0)
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}
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//
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// Check if PCIE RP Power Resource is supported or Not.
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//
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If (LEqual (GPRS (), 0)) {
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Return (0)
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}
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#if FeaturePcdGet (PcdHybridGraphicsSupported)
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//[-start-211103-IB05660186-modify]//
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If (LEqual (DGPV, NVIDIA_VID)) {
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If (LEqual (PCI_SCOPE.NVGE, NV_GEN_20)) {
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Return (DGPU_BRIDGE_SCOPE.GSTA ())
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}
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}
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//[-end-211103-IB05660186-modify]//
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#endif
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//
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// Return PCIE RP Power Resource Status.
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//
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Return (PSTA ())
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}
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Method (_ON) {
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//
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// Check if PCIE RP is available or Not by Checking Vendor and Device ID.
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//
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If (LEqual (VDID, 0xFFFFFFFF)) {
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Return ()
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}
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//
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// Check if PCIE RP Power Resource is supported or Not.
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//
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If (LEqual (GPRS (), 0)) {
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Return ()
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}
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//[-start-210816-IB05660174-add]//
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#if FeaturePcdGet (PcdHybridGraphicsSupported)
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If (LEqual (DGPV, NVIDIA_VID)) {
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If (LEqual (PCI_SCOPE.NVGE, NV_GEN_20)) {
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If (LNotEqual(DGPU_BRIDGE_SCOPE.GSTA(), Zero)) { //check the dGPU OFF?
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Return ()
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}
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}
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If (LEqual (PCI_SCOPE.TDGC, One)) {
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If (LEqual (PCI_SCOPE.DGCX, 0x03)) {
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PCI_SCOPE.GC6O ()
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} ElseIf (LEqual (PCI_SCOPE.DGCX, 0x04)) {
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PCI_SCOPE.GC6O ()
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}
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// Clear Defer flag
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Store (Zero, PCI_SCOPE.TDGC)
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Store (Zero, PCI_SCOPE.DGCX)
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} Else {
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//
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// Turn on slot power
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//
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PON ()
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//
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// Trigger L2/L3 ready exit flow in rootport - transition link to Detect
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//
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L23D ()
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Store(0x07, DGPU_BRIDGE_SCOPE.CMDR) // Enable root port cmd reg
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Store(Zero, DGPU_BRIDGE_SCOPE.D0ST) // Put root port in D0
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While (LNotEqual (DGPU_SCOPE.NVID, NVIDIA_VID)) { // Wait dGPU present on PCI bus
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Sleep (One)
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}
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Store (DGPU_SCOPE.LTRE, DGPU_BRIDGE_SCOPE.LREN) // Restore LTR enable bit
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Store (One, DGPU_BRIDGE_SCOPE.CEDR) // Clear Correctable Error bit
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Store (PCI_SCOPE.DSSV, DGPU_SCOPE.SSSV) // OEM_customize: fill SVID/SSID in DWORD
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}
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//[-start-210917-QINGLIN0068-add]//
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//[-start-210925-GEORGE0009-modify]//
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#if defined(S570_SUPPORT) || defined(S77014_SUPPORT) || defined(S77014IAH_SUPPORT)
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//[-end-210925-GEORGE0009-modify]//
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If (\_SB.PC00.LPCB.EC0.ECAV) {
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If(LEqual(Acquire(\_SB.PC00.LPCB.EC0.LfcM, 0xA000),0x0)) {
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Store(0x02, \_SB.PC00.LPCB.EC0.GATY) //enable EC polling reading GPU temprature
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Sleep(10)
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Release(\_SB.PC00.LPCB.EC0.LfcM)
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}
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}
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#endif
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//[-end-210917-QINGLIN0068-add]//
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} Else {
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#endif
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//[-end-210816-IB05660174-add]//
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//
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// Turn on slot power
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//
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PON ()
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//
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// Trigger L2/L3 ready exit flow in rootport - transition link to Detect
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//
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L23D ()
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//[-start-210915-QINGLIN0068-add]//
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#if defined(C770_SUPPORT) || defined(S370_SUPPORT)
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If (CondRefOf (DVES)) { //Only DG2 dGPU root port have this method
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If(LNotEqual (DGBA, 0)) {
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If (\_SB.PC00.LPCB.EC0.ECAV) {
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If(LEqual(Acquire(\_SB.PC00.LPCB.EC0.LfcM, 0xA000),0x0)) {
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//[start-210916-STORM1114-modify]
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//[-start-220120-QINGLIN0149-modify]//
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//#if defined(C770_SUPPORT)
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Store(0x03, \_SB.PC00.LPCB.EC0.GATY) //enable EC polling reading GPU temprature
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//#else
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// Store(0x02, \_SB.PC00.LPCB.EC0.GATY) //enable EC polling reading GPU temprature
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//#endif
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//[-end-220120-QINGLIN0149-modify]//
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//[end-210916-STORM1114-modify]
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Sleep(10)
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Release(\_SB.PC00.LPCB.EC0.LfcM)
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}
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}
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}
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}
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#endif
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//[-end-210915-QINGLIN0068-add]//
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//[-start-210816-IB05660174-add]//
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#if FeaturePcdGet (PcdHybridGraphicsSupported)
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}
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#endif
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//[-end-210816-IB05660174-add]//
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}
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Method (_OFF) {
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//
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// Check if PCIE RP is available or Not by Checking Vendor and Device ID.
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//
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If (LEqual (VDID, 0xFFFFFFFF)) {
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Return ()
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}
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//
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// Check if PCIE RP Power Resource is supported or Not.
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//
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If (LEqual (GPRS (), 0)) {
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Return ()
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}
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//[-start-210816-IB05660174-add]//
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#if FeaturePcdGet (PcdHybridGraphicsSupported)
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If (LEqual (DGPV, NVIDIA_VID)) {
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If (LEqual (PCI_SCOPE.NVGE, NV_GEN_20)) {
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If (LNotEqual(DGPU_BRIDGE_SCOPE.GSTA(), One)) { //check the dGPU ON?
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Return ()
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}
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}
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//[-start-210917-QINGLIN0068-add]//
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//[-start-210925-GEORGE0009-modify]//
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#if defined(S570_SUPPORT) || defined(S77014_SUPPORT) || defined(S77014IAH_SUPPORT)
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//[-end-210925-GEORGE0009-modify]//
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If (\_SB.PC00.LPCB.EC0.ECAV) {
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If(LEqual(Acquire(\_SB.PC00.LPCB.EC0.LfcM, 0xA000),0x0)) {
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Store(0x00, \_SB.PC00.LPCB.EC0.GATY) //disable EC polling reading GPU temprature
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Sleep(10)
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Release(\_SB.PC00.LPCB.EC0.LfcM)
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}
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}
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#endif
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//[-end-210917-QINGLIN0068-add]//
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If (LEqual (PCI_SCOPE.TDGC, One)) {
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CreateField (PCI_SCOPE.TGPC, 0, 3, GPPC) // GPU Power Control
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If (LEqual (ToInteger (GPPC), 0x01)) {
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PCI_SCOPE.GC6I ()
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} ElseIf (LEqual (ToInteger (GPPC), 0x02)) {
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PCI_SCOPE.GC6I ()
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}
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} Else {
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Store (DGPU_BRIDGE_SCOPE.LREN, DGPU_SCOPE.LTRE) // Save LTR enable bit
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//
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// Trigger L2/L3 ready entry flow in rootport
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//
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DL23 ()
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//
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// Turn off slot power
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//
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POFF ()
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}
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} Else {
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#endif
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//[-end-210816-IB05660174-add]//
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//[-start-210915-QINGLIN0068-add]//
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#if defined(C770_SUPPORT) || defined(S370_SUPPORT)
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If (CondRefOf (DVES)) { //Only DG2 dGPU root port have this method
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If(LNotEqual (DGBA, 0)) {
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If (\_SB.PC00.LPCB.EC0.ECAV) {
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If(LEqual(Acquire(\_SB.PC00.LPCB.EC0.LfcM, 0xA000),0x0)) {
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Store(0, \_SB.PC00.LPCB.EC0.GATY) //enable EC polling reading GPU temprature
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Sleep(10)
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Release(\_SB.PC00.LPCB.EC0.LfcM)
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}
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}
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}
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}
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#endif
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//[-end-210915-QINGLIN0068-add]//
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//
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// Trigger L2/L3 ready entry flow in rootport
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//
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DL23 ()
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//
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// Turn off slot power
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//
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POFF ()
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//[-start-210816-IB05660174-add]//
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#if FeaturePcdGet (PcdHybridGraphicsSupported)
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}
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#endif
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//[-end-210816-IB05660174-add]//
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}
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} // End PowerResource
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//
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// Get Permission for Power Removal.
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// Check whether or not to Disable Power Package GPIO During Device Power OFF(D3 Cold Transition).
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// Input: VOID
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//
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// @return 1 if it is Safe to Remove/Disable Power. 0 Not allow for Power Removal.
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//
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Method (GPPR, 0) {
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// If WAKP has not been defined we can safely disable power.
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// If WAKP is defined this slot does not supply device with auxilary power and we have to keep primary power
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// to allow for WAKE. If WAKP is not equal to 0 and WKEN has been enabled do not disable the power.
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If (CondRefOf (WAKP)) {
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If (LAnd (LNotEqual (WAKP, 0), LEqual (WKEN, 0))) {
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Return (0)
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}
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}
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//
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// If PCPB has not been defined we can safely disable power.
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// If PCPB is defined and non Zero we have to keep primary power.
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//
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If (CondRefOf (PCPB)) {
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If (LNotEqual (PCPB, 0)) {
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Return (0)
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}
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}
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//
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// If DVES Method has not been defined we can safely disable power.
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// If DVES Method is defined and return Zero value we have to keep primary power.
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//
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If (CondRefOf (DVES)) {
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If (LEqual (DVES (), 0)) {
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Return (0)
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}
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}
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//
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// Now Safe To Remove/Disable Power.
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//
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Return (1)
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}
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//
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// Get PCIe RP Power Resource Support.
|
|
// If D3 Cold is supported by PCIE RP or Not.
|
|
// Input: VOID
|
|
//
|
|
// @return 1 PCIE RP Power Resource Supported. 0 PCIE RP Power Resource Not Supported.
|
|
//
|
|
Method (GPRS, 0) {
|
|
|
|
If (LAnd (CondRefOf (PRTP), LEqual (PRTP, PCIE_RP_TYPE_CPU))) {
|
|
|
|
//
|
|
// Check for Hybrid Connection Status for PCIE RP and for single CPU M.2 with x2 MUX
|
|
//
|
|
If (CondRefOf (\HBCL)) {
|
|
If (LOr(LNotEqual(\HBCL, 0xFF), LLessEqual(\HBCL, 0x2))) {
|
|
If (LEqual (\HBCL, SLOT)) {
|
|
Return (0)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Check for Hybrid Connection Status for PCIE RP and for single CPU M.2 with x2 MUX
|
|
//
|
|
If (LAnd (CondRefOf (PRTP), LEqual (PRTP, PCIE_RP_TYPE_PCH))) {
|
|
If (CondRefOf (HBSL)) {
|
|
Divide ( Subtract (SLOT, 1), 4, , Local0) // Get PCIE RP Controller Number ( (SLOT-1)/4)
|
|
// Check if Hybrid Connection Status BIT Corresponding to Controller Number is SET or NOT.
|
|
If ( And (HBSL, ShiftLeft (BIT0, Local0))) {
|
|
Return (0)
|
|
}
|
|
}
|
|
|
|
If (LAnd(CondRefOf (\HBCL), CondRefOf (\HBPL))) {
|
|
If (LOr(LNotEqual(\HBCL, 0xFF), LLessEqual(\HBCL, 0x2))) {
|
|
If (LEqual (\HBPL, Subtract(SLOT, 1))) {
|
|
Return (0)
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
//
|
|
// Check if D3 Cold is supported for PCIE RP.
|
|
//
|
|
//[start-211104-STORM1118-modify]
|
|
//[start-211108-SHAONN0014-modify]
|
|
#if defined(C770_SUPPORT) || defined(S370_SUPPORT)
|
|
If (CondRefOf (DVES)) { //Only DG2 dGPU root port have this method
|
|
// DG2 support D3 Cold
|
|
} Else {
|
|
#endif
|
|
//[end-211104-STORM1118-modify]
|
|
If (CondRefOf (RD3C)) {
|
|
If (LNotEqual (RD3C, 0x02)) {
|
|
Return (0)
|
|
}
|
|
}
|
|
//[start-211104-STORM1118-modify]
|
|
#if defined(C770_SUPPORT) || defined(S370_SUPPORT)
|
|
}
|
|
#endif
|
|
//[end-211108-SHAONN0014-modify]
|
|
//[end-211104-STORM1118-modify]
|
|
//
|
|
// Check if PCIE RP is Mapped under VMD. D3 Cold flow will be taken care by VMD and it's Child ACPI Devices.
|
|
//
|
|
If (CondRefOf (PRMV)) {
|
|
If (LEqual (PRMV, 1)) {
|
|
Return (0)
|
|
}
|
|
}
|
|
|
|
//
|
|
// D3 Cold is supported for PCIE RP
|
|
//
|
|
Return (1)
|
|
}
|
|
|
|
//
|
|
// Returns the status of PCIe slot core power.
|
|
//
|
|
Method (PSTA, 0) {
|
|
|
|
//
|
|
// RESET# assertion is mandatory for PCIe RTD3
|
|
// So if RESET# is asserted the whole slot is off
|
|
//
|
|
If (\PIN.STA (RSTG)) {
|
|
Return (0)
|
|
} Else {
|
|
Return (1)
|
|
}
|
|
}
|
|
|
|
// Turn on power to PCIe Slot
|
|
// Since this method is also used by the remapped devices to turn on power to the slot
|
|
// this method should not make any access to the PCie config space.
|
|
Method (PON) {
|
|
|
|
//Check if the RP is a CEM slot
|
|
If (CondRefOf(CEMP)) {
|
|
CEMP(1) //set the CEM slot to leave D3Cold
|
|
}
|
|
// Disable WAKE
|
|
If (CondRefOf (WAKG)) {
|
|
\_SB.SHPO (WAKG, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
\_SB.CAGS (WAKG) // Clear GPIO Status if set.
|
|
}
|
|
If (CondRefOf (DHDW)) { // DG support HPD as D3 Wake GPIO and DHDW exists
|
|
DHDW () // Disable Discrete Graphics HPD SCI implementated As D3 Wake GPIO
|
|
}
|
|
|
|
// Restore power to the modPHY (Only for PCH PCIE RP)
|
|
If (LAnd (CondRefOf (PRTP), LEqual (PRTP, PCIE_RP_TYPE_PCH))) {
|
|
\_SB.PSD0 (SLOT)
|
|
}
|
|
|
|
// Turn ON Power for PCIe Slot
|
|
If (CondRefOf (PWRG)) {
|
|
// Delay by 10 ms if required using WOFF
|
|
If (CondRefOf (WOFF)) {
|
|
If (LNotEqual (WOFF, Zero)) {
|
|
Divide (Subtract (Timer (), WOFF), 10000, , Local0) // Store Elapsed time in ms, ignore remainder
|
|
If (LLess (Local0, 200)) { // If Elapsed time is less than 20ms
|
|
Sleep (Subtract (200, Local0)) // Sleep for the remaining time
|
|
}
|
|
Store (0, WOFF)
|
|
}
|
|
}
|
|
\PIN.ON (PWRG)
|
|
//[-start-210816-IB05660174-add]//
|
|
// HG power sequence tuning: delay after power enable for PCIe by DelayAfterPwrEn of SCU
|
|
// Following delay code needs to be opened by project requirement.
|
|
//Sleep (DLPW)
|
|
//[-end-210816-IB05660174-add]//
|
|
//[-start-210927-QINGLIN0086-modify]//
|
|
#if defined(S570_SUPPORT)
|
|
#if defined(NV_DGPU_PEG_PORT) && (NV_DGPU_PEG_PORT)
|
|
If(CondRefOf(PWGG))
|
|
{
|
|
Store(100, Local0) //max delay 100ms
|
|
Store(DeRefOf(Index(PWGG, 0)), Local1) //get current GPI status
|
|
Store(DeRefOf(Index(PWGG, 1)), Local2) //get active value
|
|
While(LAnd(LNotEqual(\_SB.GGIV(Local1), Local2), Local0)) //wait power good status
|
|
{
|
|
Decrement(Local0)
|
|
Sleep(1)
|
|
}
|
|
If (LNotEqual(Local0, 0)) { //power good OK
|
|
Sleep(3) //sleep 3ms after power good signel OK
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Sleep (PEP0)
|
|
}
|
|
#else
|
|
Sleep (PEP0)
|
|
#endif
|
|
//[-start-220403-TAMT000047-add]//
|
|
#elif defined(S77014IAH_SUPPORT)
|
|
#if defined(NV_DGPU_PEG_PORT) && (NV_DGPU_PEG_PORT)
|
|
If(CondRefOf(PWGG))
|
|
{
|
|
Store(100, Local0) //max delay 100ms
|
|
Store(DeRefOf(Index(PWGG, 0)), Local1) //get current GPI status
|
|
Store(DeRefOf(Index(PWGG, 1)), Local2) //get active value
|
|
While(LAnd(LNotEqual(\_SB.GGIV(Local1), Local2), Local0)) //wait power good status
|
|
{
|
|
Decrement(Local0)
|
|
Sleep(1)
|
|
}
|
|
If (LNotEqual(Local0, 0)) { //power good OK
|
|
Sleep(3) //sleep 3ms after power good signel OK
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Sleep (PEP0)
|
|
}
|
|
#else
|
|
Sleep (PEP0)
|
|
#endif
|
|
//[-end-220403-TAMT000047-add]//
|
|
#else
|
|
Sleep (PEP0)
|
|
#endif
|
|
//[-end-210927-QINGLIN0086-modify]//
|
|
}
|
|
|
|
//
|
|
// On RTD3 Exit, BIOS will instruct the PMC to Enable source clocks.
|
|
// This is done through sending a PMC IPC command if IPC Command is supported.
|
|
//
|
|
If (CondRefOf (SCLK)) {
|
|
//[-start-210927-QINGLIN0086-modify]//
|
|
#if defined(S570_SUPPORT) && defined(NV_DGPU_PEG_PORT) && (NV_DGPU_PEG_PORT)
|
|
// not need, remove it.
|
|
//[-start-220403-TAMT000047-add]//
|
|
#elif defined(S77014IAH_SUPPORT) && defined(NV_DGPU_PEG_PORT) && (NV_DGPU_PEG_PORT)
|
|
// not need, remove it.
|
|
//[-end-220403-TAMT000047-add]//
|
|
#else
|
|
If(CondRefOf(TMCS)) {
|
|
//[-start-210927-QINGLIN0086-modify]//
|
|
SPCX(SCLK, 1, TMCS)
|
|
} Else {
|
|
SPCO(SCLK, 1)
|
|
}
|
|
#endif
|
|
//[-end-210927-QINGLIN0086-modify]//
|
|
}
|
|
|
|
#if FeaturePcdGet (PcdHybridGraphicsSupported)
|
|
//[-start-211112-QINGLIN0114-modify]//
|
|
#if defined(S570_SUPPORT) && defined(NV_DGPU_PEG_PORT) && (NV_DGPU_PEG_PORT)
|
|
//Already down
|
|
//[-start-220403-TAMT000047-add]//
|
|
#elif defined(S77014IAH_SUPPORT) && defined(NV_DGPU_PEG_PORT) && (NV_DGPU_PEG_PORT)
|
|
//Already down
|
|
//[-end-220403-TAMT000047-add]//
|
|
#else
|
|
// IBV_customize ADD below for before De-Assert Reset Pin
|
|
//[-start-211103-IB05660186-modify]//
|
|
If (LEqual (DGPV, NVIDIA_VID)) {
|
|
If (LEqual (PCI_SCOPE.NVGE, NV_GEN_20)) {
|
|
Store (Zero, Local0)
|
|
While (LEqual (\_SB.GGIV (DGPU_SCOPE.PWGD), Zero)) { // OEM need add PWR_OK pin GPIO number for PWOK
|
|
If (LGreater (Local0, 0x20)) {
|
|
Store ("PON: Time Out waiting PWOK ON", Debug)
|
|
Break
|
|
}
|
|
|
|
Sleep (One)
|
|
Increment (Local0)
|
|
}
|
|
}
|
|
}
|
|
//[-end-211103-IB05660186-modify]//
|
|
#endif
|
|
//[-end-211112-QINGLIN0114-modify]//
|
|
#endif
|
|
|
|
// De-Assert Reset Pin
|
|
\PIN.OFF (RSTG)
|
|
//[-start-210816-IB05660174-add]//
|
|
// HG power sequence tuning: delay after hold reset for PCIe by DelayAfterHoldReset of SCU
|
|
// Following delay code needs to be opened by project requirement.
|
|
//Sleep (DLHR)
|
|
//[-end-210816-IB05660174-add]//
|
|
}
|
|
|
|
// Turn off power to PCIe Slot
|
|
// Since this method is also used by the remapped devices to turn off power to the slot
|
|
// this method should not make any access to the PCIe config space.
|
|
Method (POFF) {
|
|
|
|
// Assert Reset Pin after the delay passed from the bus driver
|
|
Divide (LNRD, 1000, , Local1)
|
|
Sleep (Local1)
|
|
|
|
// Reset pin is mandatory for correct PCIe RTD3 flow
|
|
\PIN.ON (RSTG)
|
|
//[-start-210816-IB05660174-add]//
|
|
// HG power sequence tuning: delay after hold reset for PCIe by DelayAfterHoldReset of SCU
|
|
// Following delay code needs to be opened by project requirement.
|
|
//Sleep (DLHR)
|
|
//[-end-210816-IB05660174-add]//
|
|
|
|
If (LAnd (CondRefOf (PRTP), LEqual (PRTP, PCIE_RP_TYPE_PCH))) {
|
|
// Enable modPHY power gating
|
|
// This must be done after the device has been put in reset
|
|
\_SB.PSD3 (SLOT)
|
|
}
|
|
|
|
//
|
|
// On RTD3 entry, BIOS will instruct the PMC to disable source clocks.
|
|
// This is done through sending a PMC IPC command if IPC Command is supported.
|
|
//
|
|
If (CondRefOf (SCLK)) {
|
|
//[-start-210927-QINGLIN0086-modify]//
|
|
#if defined(S570_SUPPORT) && defined(NV_DGPU_PEG_PORT) && (NV_DGPU_PEG_PORT)
|
|
// not need, remove it.
|
|
//[-start-220403-TAMT000047-add]//
|
|
#elif defined(S77014IAH_SUPPORT) && defined(NV_DGPU_PEG_PORT) && (NV_DGPU_PEG_PORT)
|
|
// not need, remove it.
|
|
//[-end-220403-TAMT000047-add]//
|
|
#else
|
|
If(CondRefOf(TMCS)) {
|
|
SPCX(SCLK, 0, TMCS)
|
|
} Else {
|
|
SPCO(SCLK, 0)
|
|
}
|
|
#endif
|
|
//[-end-210927-QINGLIN0086-modify]//
|
|
}
|
|
|
|
// Power OFF for Slot
|
|
If (CondRefOf (PWRG)) {
|
|
If ( LEqual ( GPPR(), 1)) { // we can safely disable power.
|
|
\PIN.OFF (PWRG)
|
|
//[-start-210927-QINGLIN0086-add]//
|
|
//[-start-220403-TAMT000047-add]//
|
|
#if defined(S570_SUPPORT) || defined(S77014IAH_SUPPORT)
|
|
//[-end-220403-TAMT000047-add]//
|
|
#if defined(NV_DGPU_PEG_PORT) && (NV_DGPU_PEG_PORT)
|
|
Sleep (100) //sleep 100ms
|
|
#endif
|
|
#endif
|
|
//[-end-210927-QINGLIN0086-add]//
|
|
//[-start-210816-IB05660174-add]//
|
|
// HG power sequence tuning: delay after power enable for PCIe by DelayAfterPwrEn of SCU
|
|
// Following delay code needs to be opened by project requirement.
|
|
//Sleep (DLPW)
|
|
//[-end-210816-IB05660174-add]//
|
|
}
|
|
// Store current timestamp in WOFF
|
|
If (CondRefOf (WOFF)) {
|
|
Store (Timer (), WOFF)
|
|
}
|
|
}
|
|
|
|
// enable WAKE
|
|
If (CondRefOf (WAKG)) {
|
|
If (LAnd (LNotEqual (WAKG, 0), WKEN)) {
|
|
\_SB.SHPO (WAKG, 0)
|
|
}
|
|
}
|
|
If (CondRefOf (EHDW)) { // DG support HPD as D3 Wake GPIO and DHDW exists
|
|
EHDW () // Enable Discrete Graphics HPD SCI implementated As D3 Wake GPIO
|
|
}
|
|
//Check if the RP is a CEM slot
|
|
If (CondRefOf(CEMP)) {
|
|
CEMP(0) //Set the CEM slot to enter D3cold
|
|
}
|
|
}
|
|
|
|
Method (_PR0) {
|
|
Return (Package (){PXP})
|
|
}
|
|
|
|
Method (_PR3) {
|
|
Return (Package (){PXP})
|
|
}
|
|
|
|
//
|
|
// Update PERST# assertion delay.
|
|
// This function will be called from reference code during PCIe _DSM function index 11 evaluation.
|
|
// Arg0 - New delay value in microseconds. Max is 10ms
|
|
//
|
|
// @return Last sucessfully negotiated value in us. 0 if no such value exists.
|
|
//
|
|
Method (UPRD, 1, Serialized) {
|
|
If (LLessEqual (Arg0, 10000)) {
|
|
// If the value does not exceed the limit
|
|
// Update last negotiated value and calculate the value in ms.
|
|
Store (Arg0, LNRD)
|
|
}
|
|
Return (LNRD)
|
|
}
|
|
|