633 lines
16 KiB
Plaintext
633 lines
16 KiB
Plaintext
/** @file
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ACPI RTD3 SSDT table for Thunderbolt
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2011 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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/// @details
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/// Code in this file uses following variables:
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/// SCLK: ICC Clock number - optional
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/// WAKG: WAKE GPIO pad - optional
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/// Below objects should be defined according to the format described in PinDriverLib.asl
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/// RSTG: reset pin definition - mandatory
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/// PWRG: power GPIO pad - optional
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/// WAKP: Flag to indicate that power gating must not be performed if WAKE is enabled - optional
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/// @defgroup pcie_scope PCIe Root Port Scope **/
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#define DTBT_TYPE_PCH 0x01
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#define TBT_DATA_WIDTH 4 // This represent DATA WIDTH for Each TBT Controller in a Variable
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External(\MMRP, MethodObj)
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External(\MMTB, MethodObj)
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External(PDOF, MethodObj)
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External(PDON, MethodObj)
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External(\TVCF, MethodObj)
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External(\TVRF, MethodObj)
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//
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// AcpiPinDriverLib imports(from DSDT in platform)
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//
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External(\PIN.STA, MethodObj)
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External(\PIN.ON, MethodObj)
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External(\PIN.OFF, MethodObj)
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//
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// GpioLib imports(DSDT)
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//
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External(\_SB.SHPO, MethodObj)
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//
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// HSIO lib imports
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//
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External(\_SB.PSD0, MethodObj)
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External(\_SB.PSD3, MethodObj)
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//
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// External decalarations for optional objects.
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// Defined by board specific code.
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//
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External(WAKG) //WAKE GPIO pad
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External(PWRG)
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External(SCLK)
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External(WAKP)
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External(TUID)
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External(PSON)
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External(TBDC)
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External(NCB7)
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External(LASX)
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External(D3HT)
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External(L23E)
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External(L23R)
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External(DPGE)
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External(HPEX)
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External(PMEX)
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External(HPSX)
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External(PMSX)
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External(PDCX)
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External(PDSX)
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External(PSPX)
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External(TRDO)
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External(TRD3)
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External(TBPE)
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External(TOFF)
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External(TEDC)
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External(PCPB) // PCIe core power veto bitmask, default 0 - allow for core power removal
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Name(G2SD, 0) // Go2Sx done, set by GO2S, cleaned by _ON
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Name(RSTF, 0) // Reset Flag
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Name(CSEN, 0) // If enable wait for RTD3 Exit command respond in _PS0() method
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Name(PSHR, 0) // Global Variable to Save Power State Value of TBT HR
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Name(WKEN, 0) // WAKE enable on PCIe device.
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Method(_S0W, 0, Serialized) {
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Return(4)
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}
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//
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// TBT Debug Method - Scan hierarchy
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//
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Method(TSCH, 0, Serialized) {
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Store (\MMTB (SLOT, DTBT_TYPE_PCH), Local7)
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// TODO Make one generic copy
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OperationRegion(TBDM, SystemMemory, Local7, 0x550)// TBT HR PCICFG MMIO
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Field(TBDM,DWordAcc, NoLock, Preserve) {
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DIVI, 32,
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CMDR, 32,
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Offset(0x84),
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TBPS, 2, // PowerState of TBT
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Offset(0x548),
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TB2P, 32,
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P2TB, 32
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}
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If(LNotEqual(VDID,0xFFFFFFFF)) {
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}
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If(LNotEqual(DIVI,0xFFFFFFFF)) {
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}
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Add(Local7, 0x00108000, Local7) // Advance 1 Bus 1 Dev No. Bus N+1 Device 1
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OperationRegion(TDS0, SystemMemory, Local7, 0x100)// TBT DS0 PCICFG MMIO
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Field(TDS0,DWordAcc, NoLock, Preserve) {
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Offset (0),
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P0ID, 32,
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Offset(0xD0),
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, 29,
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LAI0, 1, // PCIe Link Active Indicator of DS port 0
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Offset(0xD8),
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, 19,
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PDC0, 1, // PCIe Presence Detect Changed Indicator of DS port 0
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, 2,
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PDS0, 1, // PCIe Presence Detect State Indicator of DS port 0
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}
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If(LNotEqual(P0ID,0xFFFFFFFF)) {
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}
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Add(Local7, 0x00010000, Local7) // Advacne 2 Dev No. Bus N+1 Device 3
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OperationRegion(TDS1, SystemMemory, Local7, 0x100)// TBT DS1 PCICFG MMIO
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Field(TDS1,DWordAcc, NoLock, Preserve) {
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Offset (0),
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P1ID, 32,
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Offset(0xD0),
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, 29,
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LAI1, 1, // PCIe Link Active Indicator of DS port 1
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Offset(0xD8),
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, 19,
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PDC1, 1, // PCIe Presence Detect Changed Indicator of DS port 1
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, 2,
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PDS1, 1, // PCIe Presence Detect State Indicator of DS port 1
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}
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If(LNotEqual(P1ID,0xFFFFFFFF)) {
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}
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TVAL()
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}
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//
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// TBT Debug Method - Dump All Variables
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//
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Method(TVAL, 0, Serialized) {
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}
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Method (PPS0, 0, Serialized) { // Platform specific PCIe root port _PS0 Hook Function.
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TSCH()
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if (LEqual (CSEN, 1)) {
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Store (\MMRP (SLOT, DTBT_TYPE_PCH), Local7)
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OperationRegion(L23P,SystemMemory,Local7,0x100)
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Field(L23P,WordAcc, NoLock, Preserve)
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{
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Offset(0xA4),// PMCSR
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D3HT, 2, // PowerState
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}
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CSPL ()
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Store (0, CSEN) // Disable _PS0 once called
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Store (PSHR, D3HT) // Store Back D3HT value
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Store (0, PSHR)
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}
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TSCH()
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}
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Method(PPS3, 0, Serialized) { // Platform specific PCIe root port _PS3 Hook Function.
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TSCH()
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}
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Method (_DSD, 0) {
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Return (
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Package () {
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ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
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Package () {
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Package (2) {"HotPlugSupportInD3", 1},
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},
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ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"),
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Package () {
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Package (2) {"ExternalFacingPort", 1}, // Property 1: This is a TBT/CIO port
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Package (2) {"UID", TUID}, // Property 2: UID of the TBT RP on platform, range is: 0, 1, ..., NumOfTBTRP - 1
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}
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}
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) // End of Return ()
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}
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Method(_DSW, 3)
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{
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/// This method is used to enable/disable wake from PCIe (WKEN)
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If (LGreaterEqual(Arg1, 1)) { /// If entering Sx, need to disable WAKE# from generating runtime PME also set 2 to TOFF.
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Store(0, WKEN)
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Store (TVCF (TUID, 2, TBT_DATA_WIDTH, TOFF), TOFF)
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} Else { /// If Staying in S0
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If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake
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{ ///- Set PME
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Store (1, WKEN)
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Store (TVCF (TUID, 1, TBT_DATA_WIDTH, TOFF), TOFF)
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} Else { ///- Disable runtime PME, either because staying in D0 or disabling wake
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Store (0, WKEN)
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Store (TVCF (TUID, 0, TBT_DATA_WIDTH, TOFF), TOFF)
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}
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}
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/** @defgroup pcie_dsw PCIE _DSW **/
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} // End _DSW
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//
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// PCIe slot power resource definition
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//
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PowerResource(PXP, 0, 0) {
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Method(_STA, 0) {
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If (LEqual (VDID, 0xFFFFFFFF)) {
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Return(0)
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}
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Return(PSTA())
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}
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Method(_ON) {
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//Store (TVCF (TUID, 1, TBT_DATA_WIDTH, TRDO), TRDO)
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TSCH()
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PON()
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//Store (TVCF (TUID, 0, TBT_DATA_WIDTH, TRDO), TRDO)
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TSCH()
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}
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Method(_OFF) {
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//Store (TVCF (TUID, 0, TBT_DATA_WIDTH, TRD3), TRD3)
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TSCH()
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POFF()
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//Store (TVCF (TUID, 1, TBT_DATA_WIDTH, TRD3), TRD3)
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TSCH()
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}
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}
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//
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// Returns the status of PCIe slot core power
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//
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Method(PSTA, 0) {
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//
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// RESET# assertion is mandatory for PCIe RTD3
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// So if RESET# is asserted the whole slot is off
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//
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If(\PIN.STA(RSTG)) {
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Return(0)
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} Else {
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Return (1)
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}
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}
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Method (CSEX, 0, Serialized) {
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Store (\MMTB (SLOT, DTBT_TYPE_PCH), Local7)
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OperationRegion(TBDI, SystemMemory, Local7, 0x550)// TBT HR PCICFG MMIO
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Field(TBDI,DWordAcc, NoLock, Preserve) {
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DIVI, 32,
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CMDR, 32,
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Offset(0x548),
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TB2P, 32,
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P2TB, 32
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}
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Store(200, Local1)
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Store(0x0209, P2TB) // Write SX_EXIT_TBT_CONNECTED to PCIe2TBT with Data parameter = 0x02 (TBT RTD3 EXIT Command)
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While (LGreater(Local1, 0)) {
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Store(Subtract(Local1, 1), Local1)
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Store(TB2P, Local2)
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If(LAnd(LEqual(Local2, 0xFFFFFFFF), LEqual(Local1, 0x1))) // Device gone
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{
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Return(0)
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}
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If(LAnd(LNotEqual(Local2, 0xFFFFFFFF), And(Local2, 1))) // Done
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{
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break
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}
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Sleep(5)
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}
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Store(0x0, P2TB) // Write 0 to PCIe2TBT
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Return (1)
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} // End of Method(CSEX, 0, Serialized)
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Method (CSPL, 0, Serialized) {
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Store (\MMTB (SLOT, DTBT_TYPE_PCH), Local7)
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OperationRegion(TBDI, SystemMemory, Local7, 0x550)// TBT HR PCICFG MMIO
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Field(TBDI,DWordAcc, NoLock, Preserve) {
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DIVI, 32,
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CMDR, 32,
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Offset(0x548),
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TB2P, 32,
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P2TB, 32
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}
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// Fast Link bring-up flow
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Store(500, Local1)
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While (LGreater(Local1, 0)) {
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Store(Subtract(Local1, 1), Local1)
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Store(TB2P, Local2)
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If (LEqual(Local2, 0xFFFFFFFF)) {// Device gone
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Return()
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}
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If (LNotEqual(DIVI, 0xFFFFFFFF)) {
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break
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}
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Sleep(10)
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}
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} // End of Method(CSPL, 0, Serialized)
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Method(PON, 0, Serialized) /// Turn on core power to PCIe Slot
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{
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Store (\MMTB (SLOT, DTBT_TYPE_PCH), Local6)
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OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG MMIO
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Field(TBDI,DWordAcc, NoLock, Preserve) {
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DIVI, 32,
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CMDR, 32,
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Offset(0x84),
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TBPS, 2, // PowerState of TBT
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Offset(0x548),
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TB2P, 32,
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P2TB, 32
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}
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// Check RTD3 power enable, if already ON, no need to execute sx_exit
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If (TVRF (TUID, TBT_DATA_WIDTH, TBPE)) {
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Return()
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}
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Store(0,G2SD)
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//
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// dTBT special requirement on RTD3 exit:
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// 1. Guarantee that PCIe clock is running - MR clock request is asserted and BIOS can unmask the request and plus custom delay.
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// 2. Toggle RTD3 pin - This will indicate to MR that it can reset the PHY. Reset of the PHY requires a running clock.
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// 3. After 10ms de-assert the PERST (same as done today)
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//
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//
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// On RTD3 Exit, BIOS will instruct the PMC to Enable source clocks.
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// This is done through sending a PMC IPC command.
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//
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If (CondRefOf (\DTRC)) {
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If (\DTRC) {
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/// de-assert CLK_REQ MSK
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If (CondRefOf (SCLK)) {
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SPCO (SCLK, 1)
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}
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If (CondRefOf (\DTRD)) {
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Sleep (\DTRD)
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}
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}
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}
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/// Turn ON Power for PCIe Slot
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If (CondRefOf (PWRG)) {
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\PIN.ON (PWRG)
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Sleep (PEP0)
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}
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/// De-Assert Reset Pin
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\PIN.OFF(RSTG)
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Store(0, RSTF) // Clear Reset Flag
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Store(TVCF (TUID, 1, TBT_DATA_WIDTH, TBPE), TBPE)
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L23D()
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// Check if any TBT Endpoint Device was connected, if no TBT Endpoint Device is Connected, no need to execute sx_exit
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If (LEqual (TVRF (TUID, TBT_DATA_WIDTH, TEDC), 0)) {
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Return()
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}
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// TBT special sleep.
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Store (D3HT, PSHR) // Save D3HT Value to PSHR Global Variable
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Store (0, D3HT)// D0
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Store (20, Local2) // Poll for TBT, up to 200 ms
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While (LGreater(Local2, 0)) {
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Store(Subtract(Local2, 1), Local2)
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Store(TB2P, Local3)
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If (LNotEqual(Local3, 0xFFFFFFFF)) { // Done
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break
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}
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Sleep(10)
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}
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TSCH()
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If (LLessEqual(Local2, 0)) {
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}
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If ( LEqual (CSEX(), 1)) {
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If (CondRefOf (TBDC)) {
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If (LGreater (TBDC, 0)) {
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CSPL ()
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} else {
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Store (1, CSEN)
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}
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}
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} // If ( LEqual (CSEX(), 1))
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if (LEqual(CSEN, 0)) {
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Store (PSHR, D3HT) // Store Back D3HT value
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}
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If(CondRefOf(PDON)) {
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PDON()
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}
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} // End of ON
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Method(POFF, 0, Serialized) { /// Turn off core power to PCIe Slot
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If (LEqual (TVRF (TUID, TBT_DATA_WIDTH, TOFF), 0)) {
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Return()
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}
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Store (\MMTB (SLOT, DTBT_TYPE_PCH), Local6)
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OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG MMIO
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Field(TBDI,DWordAcc, NoLock, Preserve) {
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DIVI, 32,
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CMDR, 32,
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Offset(0x84),
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TBPS, 2, // PowerState of TBT
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Offset(0x548),
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TB2P, 32,
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P2TB, 32
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}
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Add(Local6, 0x00108000, Local6) // Advance 1 Bus 1 Dev No. Bus N+1 Device 1
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OperationRegion(DSP0, SystemMemory, Local6, 0x100)// TBT DS0 PCICFG MMIO
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Field(DSP0,DWordAcc, NoLock, Preserve) {
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Offset (0),
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P0ID, 32,
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Offset(0xD0),
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, 29,
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LAI0, 1, // PCIe Link Active Indicator of DS port 0
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Offset(0xD8),
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, 19,
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PDC0, 1, // PCIe Presence Detect Changed Indicator of DS port 0
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, 2,
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PDS0, 1, // PCIe Presence Detect State Indicator of DS port 0
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}
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Add(Local6, 0x00010000, Local6) // Advacne 2 Dev No. Bus N+1 Device 3
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OperationRegion(DSP1, SystemMemory, Local6, 0x100)// TBT DS1 PCICFG MMIO
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Field(DSP1,DWordAcc, NoLock, Preserve) {
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Offset (0),
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P1ID, 32,
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Offset(0xD0),
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, 29,
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LAI1, 1, // PCIe Link Active Indicator of DS port 1
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Offset(0xD8),
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, 19,
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PDC1, 1, // PCIe Presence Detect Changed Indicator of DS port 1
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, 2,
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PDS1, 1, // PCIe Presence Detect State Indicator of DS port 1
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}
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If (Lgreater(TVRF (TUID, TBT_DATA_WIDTH, TOFF), 1)) {
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Store (TVCF (TUID, 0, TBT_DATA_WIDTH, TOFF), TOFF)
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Store(1, RSTF) // Set Reset Flag
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Return()
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}
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Store(D3HT, Local1)
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Store(0, D3HT)// D0
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Store(P2TB, Local3)
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Store (TVCF (TUID, 0, TBT_DATA_WIDTH, TOFF), TOFF)
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Sleep(10)
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Store(TBPS, Local6)
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Store(0, TBPS)
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Sleep(10)
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Store(PDS0, Local2) // Store Device Presence under DS0
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Store(PDS1, Local3) // Store Device Presence under DS1
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TSCH()
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If(LAnd(LNotEqual(P0ID, 0xFFFFFFFF), LNotEqual(P1ID, 0xFFFFFFFF))) {
|
|
If(LOr(LEqual(PDC0, 1), LEqual(PDC1, 1))) {
|
|
Notify (^, 0)
|
|
Return()
|
|
}
|
|
}
|
|
|
|
// Updating TEDC value if any TBT Endpoint device is connected behind TUID TBT Controller.
|
|
Store (TVCF (TUID, Or (PDS0, PDS1), TBT_DATA_WIDTH, TEDC), TEDC)
|
|
Store(Local6, TBPS)
|
|
Store(Local1, D3HT) // Back to Local1
|
|
DL23()
|
|
|
|
// Assert Reset Pin
|
|
// Reset pin is mandatory for correct PCIe RTD3 flow
|
|
\PIN.ON(RSTG)
|
|
Store(1, RSTF) // Set Reset Flag
|
|
|
|
//
|
|
// On RTD3 entry, BIOS will instruct the PMC to disable source clocks.
|
|
// This is done through sending a PMC IPC command.
|
|
//
|
|
If (\DTRC) {
|
|
/// assert CLK_REQ MSK
|
|
If (CondRefOf (SCLK)) {
|
|
SPCO (SCLK, 0)
|
|
}
|
|
If (CondRefOf (\DTRD)) {
|
|
Sleep (\DTRD)
|
|
}
|
|
}
|
|
Sleep (10)
|
|
|
|
/// Power OFF for TBT
|
|
If(CondRefOf(PWRG)) {
|
|
// If WAKP has not been defined we can safely disable power.
|
|
// If WAKP is defined this slot does not supply device with auxilary power and we have to keep primary power
|
|
// to allow for WAKE. If WAKP is not equal to 0 and WKEN has been enabled do not disable the power.
|
|
If(CondRefOf (WAKP)) {
|
|
If(LOr(LEqual(WAKP, 0), LNot(WKEN))) {
|
|
If(CondRefOf(PCPB)) {
|
|
If(LEqual(PCPB, 0)) {
|
|
\PIN.OFF(PWRG)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
\PIN.OFF(PWRG)
|
|
}
|
|
} Else {
|
|
}
|
|
} Else {
|
|
If(CondRefOf(PCPB)) {
|
|
If(LEqual(PCPB, 0)) {
|
|
\PIN.OFF(PWRG)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
\PIN.OFF(PWRG)
|
|
}
|
|
}
|
|
}
|
|
|
|
// enable WAKE
|
|
If(CondRefOf (WAKG)) {
|
|
If(LAnd(LNotEqual(WAKG, 0), WKEN)) {
|
|
\_SB.SHPO(WAKG, 0)
|
|
}
|
|
}
|
|
|
|
Store(TVCF (TUID, 0, TBT_DATA_WIDTH, TBPE), TBPE)
|
|
|
|
If (LEqual(\DTOE, 0)) { // Optimization not enabled, Sleep (DTRO)
|
|
Sleep (\DTRO)
|
|
} Else {
|
|
If (LOr(LEqual(Local2, 1), LEqual(Local3, 1))) { // If there is a device present under DS0 or DS1, Sleep(DTRO)
|
|
Sleep (\DTRO)
|
|
} Else { // Otherwise, Sleep (1000)
|
|
Sleep (1000)
|
|
}
|
|
}
|
|
If(CondRefOf(PDOF)) {
|
|
If (PSON) {
|
|
PDOF()
|
|
}
|
|
}
|
|
|
|
} // End of Method_OFF
|
|
|
|
Method (NFRP, 0, Serialized) /// Notify root port
|
|
{
|
|
|
|
If (LEqual (VDID, 0xFFFFFFFF))
|
|
{
|
|
Return ()
|
|
}
|
|
|
|
Store (0, Local1)
|
|
Store (0, Local2)
|
|
If (LEqual (\DTFS, 0x01)) {// if Thunderbolt(TM) support is enabled
|
|
Store (0, HPEX) //Hot Plug SCI Disable
|
|
Store (0, PMEX) //Power Management SCI Enable
|
|
|
|
Notify (^, 0)
|
|
If (LEqual (PMSX, 1)) { //clear the PME SCI status bit
|
|
Store (1, Local2)
|
|
}
|
|
Notify (^, 2)
|
|
Store (1, Local1) // Enable clear status bit
|
|
}
|
|
|
|
If (LEqual (Local1, 1))
|
|
{
|
|
Store (1, HPSX)
|
|
If (LEqual (Local2, 1)) {
|
|
Store (1, PMSX)
|
|
}
|
|
}
|
|
}
|
|
|