352 lines
9.8 KiB
Plaintext
352 lines
9.8 KiB
Plaintext
/**@file
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VMD device description
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2019 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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External(\_SB.PC00.VMD0, DeviceObj)
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If(LAnd(CondRefOf(VMDE),CondRefOf(\_SB.PC00.VMD0))) {
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Scope(\_SB.PC00)
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{
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If(LEqual(VMDE,1)) {
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Scope(VMD0) {
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External(RP01, DeviceObj)
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External(RP02, DeviceObj)
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External(RP03, DeviceObj)
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External(RP04, DeviceObj)
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External(RP05, DeviceObj)
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External(RP06, DeviceObj)
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External(RP07, DeviceObj)
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External(RP08, DeviceObj)
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External(RP09, DeviceObj)
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External(RP10, DeviceObj)
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External(RP11, DeviceObj)
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External(RP12, DeviceObj)
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External(RP13, DeviceObj)
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External(RP14, DeviceObj)
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External(RP15, DeviceObj)
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External(RP16, DeviceObj)
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External(RP17, DeviceObj)
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External(RP18, DeviceObj)
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External(RP19, DeviceObj)
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External(RP20, DeviceObj)
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External(RP21, DeviceObj)
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External(RP22, DeviceObj)
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External(RP23, DeviceObj)
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External(RP24, DeviceObj)
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External(RP25, DeviceObj)
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External(RP26, DeviceObj)
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External(RP27, DeviceObj)
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External(RP28, DeviceObj)
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External(PEG0, DeviceObj)
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External(PEG1, DeviceObj)
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External(PEG2, DeviceObj)
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External(PEG3, DeviceObj)
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External(PRT0, DeviceObj)
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External(PRT1, DeviceObj)
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External(PRT2, DeviceObj)
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External(PRT3, DeviceObj)
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External(PRT4, DeviceObj)
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External(PRT5, DeviceObj)
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External(PRT6, DeviceObj)
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External(PRT7, DeviceObj)
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External(VMR1)
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External(VMR2)
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External(VMR3)
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External(VMR4)
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External(VMCP)
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External(VMS0)
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External(HBSL)
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If(LAnd(CondRefOf(VMR1),CondRefOf(HBSL))) {
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If(LAnd((VMR1 & 0x01),LNot((HBSL & 0x01)))) {
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Scope(RP01) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR1 & 0x02),LNot((HBSL & 0x01)))) {
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Scope(RP02) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR1 & 0x04),LNot((HBSL & 0x01)))) {
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Scope(RP03) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR1 & 0x08),LNot((HBSL & 0x01)))) {
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Scope(RP04) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR1 & 0x10),LNot((HBSL & 0x02)))) {
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Scope(RP05) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR1 & 0x20),LNot((HBSL & 0x02)))) {
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Scope(RP06) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR1 & 0x40),LNot((HBSL & 0x02)))) {
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Scope(RP07) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR1 & 0x80),LNot((HBSL & 0x02)))) {
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Scope(RP08) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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}
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If(LAnd(CondRefOf(VMR2),CondRefOf(HBSL))) {
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If(LAnd((VMR2 & 0x01),LNot((HBSL & 0x04)))) {
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Scope(RP09) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR2 & 0x02),LNot((HBSL & 0x04)))) {
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Scope(RP10) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR2 & 0x04),LNot((HBSL & 0x04)))) {
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Scope(RP11) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR2 & 0x08),LNot((HBSL & 0x04)))) {
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Scope(RP12) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR2 & 0x10),LNot((HBSL & 0x08)))) {
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Scope(RP13) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR2 & 0x20),LNot((HBSL & 0x08)))) {
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Scope(RP14) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR2 & 0x40),LNot((HBSL & 0x08)))) {
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Scope(RP15) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR2 & 0x80),LNot((HBSL & 0x08)))) {
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Scope(RP16) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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}
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If(LAnd(CondRefOf(VMR3),CondRefOf(HBSL))) {
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If(LAnd((VMR3 & 0x01),LNot((HBSL & 0x10)))) {
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Scope(RP17) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR3 & 0x02),LNot((HBSL & 0x10)))) {
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Scope(RP18) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR3 & 0x04),LNot((HBSL & 0x10)))) {
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Scope(RP19) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR3 & 0x08),LNot((HBSL & 0x10)))) {
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Scope(RP20) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR3 & 0x10),LNot((HBSL & 0x20)))) {
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Scope(RP21) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR3 & 0x20),LNot((HBSL & 0x20)))) {
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Scope(RP22) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR3 & 0x40),LNot((HBSL & 0x20)))) {
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Scope(RP23) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR3 & 0x80),LNot((HBSL & 0x20)))){
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Scope(RP24) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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}
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If(LAnd(CondRefOf(VMR4),CondRefOf(HBSL))) {
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If(LAnd((VMR4 & 0x01),LNot((HBSL & 0x40)))) {
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Scope(RP25) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR4 & 0x02),LNot((HBSL & 0x40)))) {
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Scope(RP26) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR4 & 0x04),LNot((HBSL & 0x40)))) {
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Scope(RP27) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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If(LAnd((VMR4 & 0x08),LNot((HBSL & 0x40)))) {
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Scope(RP28) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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}
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If(CondRefOf(VMCP)) {
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// P.E.G. Root Port D1F0
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If(VMCP & 0x1) {
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Scope(PEG1) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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// P.E.G. Root Port D1F1
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If(LOr((VMCP & 0x2), (VMCP & 0x10))) {
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Scope(PEG2) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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// P.E.G. Root Port D1F2
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If(VMCP & 0x4) {
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Scope(PEG3) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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// P.E.G. Root Port D6F0
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If(VMCP & 0x8) {
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Scope(PEG0) {
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Include("Rtd3VmdPciePort.asl")
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}
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}
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}
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If(CondRefOf(VMS0)) {
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// SATA Controller 0 ATA Port 0
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If(VMS0 & 0x01) {
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Scope(PRT0) {
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Include("Rtd3VmdSataPort.asl")
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}
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}
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// SATA Controller 0 ATA Port 1
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If(VMS0 & 0x02) {
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Scope(PRT1) {
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Include("Rtd3VmdSataPort.asl")
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}
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}
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// SATA Controller 0 ATA Port 2
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If(VMS0 & 0x04) {
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Scope(PRT2) {
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Include("Rtd3VmdSataPort.asl")
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}
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}
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// SATA Controller 0 ATA Port 3
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If(VMS0 & 0x08) {
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Scope(PRT3) {
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Include("Rtd3VmdSataPort.asl")
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}
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}
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// SATA Controller 0 ATA Port 4
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If(VMS0 & 0x10) {
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Scope(PRT4) {
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Include("Rtd3VmdSataPort.asl")
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}
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}
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// SATA Controller 0 ATA Port 5
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If(VMS0 & 0x20) {
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Scope(PRT5) {
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Include("Rtd3VmdSataPort.asl")
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}
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}
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// SATA Controller 0 ATA Port 6
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If(VMS0 & 0x40) {
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Scope(PRT6) {
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Include("Rtd3VmdSataPort.asl")
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}
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}
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// SATA Controller 0 ATA Port 7
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If(VMS0 & 0x80) {
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Scope(PRT7) {
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Include("Rtd3VmdSataPort.asl")
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}
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}
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}
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}
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}
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}
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}
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