100 lines
4.0 KiB
Plaintext
100 lines
4.0 KiB
Plaintext
/** @file
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ACPI minimum DSDT table
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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DefinitionBlock (
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"DSDT.aml",
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"DSDT",
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0x01, // DSDT revision.
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// A Revision field value greater than or equal to 2 signifies that integers
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// declared within the Definition Block are to be evaluated as 64-bit values
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"INTEL ", // OEM ID (6 byte string)
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"TGL ",// OEM table ID (8 byte string)
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0x00 // OEM version of DSDT table (4 byte Integer)
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)
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// BEGIN OF ASL SCOPE
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{
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Scope(\_SB) {
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//---------------------------------------------------------------------------
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// Begin PCI tree object scope
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//---------------------------------------------------------------------------
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Device(PC00) { // PCI Bridge "Host Bridge"
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Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
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Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
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Name(_SEG, 0)
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Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
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Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
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Name(_UID, 0x0000) // Unique Bus ID, optional
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Name(BUF0,ResourceTemplate()
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{
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//
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// I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
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//
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DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
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0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
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//
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// PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
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//
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Io(Decode16,0x0CF8,0x0CF8,1,0x08)
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//
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// PCI MMIO space
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
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ReadWrite,0x00,0x00,0x00,0x00,0x00,,,PM01)
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})
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Method(_CRS,0,Serialized)
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{
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//
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// Create pointers to Memory Sizing values.
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//
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CreateDwordField(BUF0, ^PM01._MIN,M1MN)
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CreateDwordField(BUF0, ^PM01._MAX,M1MX)
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CreateDwordField(BUF0, ^PM01._LEN,M1LN)
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//
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// Set Memory Size Values. TLUD represents bits 31:20 of phyical
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// TOM, so shift these bits into the correct position and fix up
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// the Memory Region available to PCI.
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//
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Subtract (FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdPciReservedMemBase),M1LN)
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Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN)
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Subtract (FixedPcdGet32(PcdPciReservedMemLimit), 1, M1MX)
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Return(BUF0)
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}
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}
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}
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}// End of ASL File
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