558 lines
22 KiB
Plaintext
558 lines
22 KiB
Plaintext
## @file
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#
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#******************************************************************************
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#* Copyright 2021 Insyde Software Corp. All Rights Reserved.
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#*
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#* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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#* transmit, broadcast, present, recite, release, license or otherwise exploit
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#* any part of this publication in any form, by any means, without the prior
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#* written permission of Insyde Software Corp.
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#*
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#******************************************************************************
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## @file
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# Board description file updates configuration (PCD) settings by if-statement for this project.
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#
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# @copyright
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# INTEL CONFIDENTIAL
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# Copyright 2020 - 2021 Intel Corporation.
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#
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# The source code contained or described herein and all documents related to the
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# source code ("Material") are owned by Intel Corporation or its suppliers or
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# licensors. Title to the Material remains with Intel Corporation or its suppliers
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# and licensors. The Material may contain trade secrets and proprietary and
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# confidential information of Intel Corporation and its suppliers and licensors,
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# and is protected by worldwide copyright and trade secret laws and treaty
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# provisions. No part of the Material may be used, copied, reproduced, modified,
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# published, uploaded, posted, transmitted, distributed, or disclosed in any way
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# without Intel's prior express written permission.
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#
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# No license under any patent, copyright, trade secret or other intellectual
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# property right is granted to or conferred upon you by disclosure or delivery
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# of the Materials, either expressly, by implication, inducement, estoppel or
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# otherwise. Any license under such intellectual property rights must be
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# express and approved by Intel in writing.
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#
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# Unless otherwise agreed by Intel in writing, you may not remove or alter
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# this notice or any other notice embedded in Materials by Intel or
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# Intel's suppliers or licensors in any way.
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#
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# This file contains a 'Sample Driver' and is licensed as such under the terms
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# of your license agreement with Intel or your vendor. This file may be modified
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# by the user, subject to the additional terms of the license agreement.
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#
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# @par Specification
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##
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[PcdsFeatureFlag]
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
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gBoardModuleTokenSpaceGuid.PcdUefiShellEnable|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
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gBoardModuleTokenSpaceGuid.PcdSecurityEnable|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
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gBoardModuleTokenSpaceGuid.PcdAdvancedFeatureEnable|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 7
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gBoardModuleTokenSpaceGuid.PcdOptimizationEnable|TRUE
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!endif
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!if gBoardModuleTokenSpaceGuid.PcdSecurityEnable == TRUE
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gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
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!if $(TARGET) == DEBUG
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gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
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!endif
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!endif #PcdSecurityEnable
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!if gBoardModuleTokenSpaceGuid.PcdOptimizationEnable == TRUE
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gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|TRUE
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!endif #PcdOptimizationEnable
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gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE #LegacyVideoRom.bin and IntelGopDriver.efi
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!if gBoardModuleTokenSpaceGuid.PcdAdvancedFeatureEnable == TRUE
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gNhltFeaturePkgTokenSpaceGuid.PcdNhltFeatureEnable|TRUE
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!endif
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# XmlCli: Update Pcd Value
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gXmlCliFeaturePkgTokenSpaceGuid.PcdXmlCliFeatureEnable|TRUE
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[PcdsFixedAtBuild]
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#
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# Setting feature PCDs based on boot stages set above
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#
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
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gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
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gBoardModuleTokenSpaceGuid.PcdAcpiDebugFeatureEnable|TRUE
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!endif #PcdBootToShellOnly
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!if gBoardModuleTokenSpaceGuid.PcdAdvancedFeatureEnable == TRUE
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gBoardModuleTokenSpaceGuid.PcdGopConfigBin|FALSE
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gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
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!if gSiPkgTokenSpaceGuid.PcdAdlLpSupport == TRUE
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gSiPkgTokenSpaceGuid.PcdITbtEnable|TRUE
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!else
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gSiPkgTokenSpaceGuid.PcdITbtEnable|FALSE
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!endif
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gSiPkgTokenSpaceGuid.PcdBtgTxtLegacyPkgEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported|TRUE
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gPlatformModuleTokenSpaceGuid.PcdBeepStatusCodeEnable|FALSE
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gPlatformModuleTokenSpaceGuid.PcdPostCodeStatusCodeEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdTraceHubPostCodeEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdHgEnable|TRUE
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gBoardModuleTokenSpaceGuid.PcdS4Enable|TRUE
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gBoardModuleTokenSpaceGuid.PcdNvmeEnable|TRUE
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gBoardModuleTokenSpaceGuid.PcdIntelRaidEnable|TRUE
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gBoardModuleTokenSpaceGuid.PcdTerminalEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0
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#[-start-200420-IB17800066-modify]#
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gSiPkgTokenSpaceGuid.PcdAmtEnable|$(AMT_ENABLE)
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#[-end-200420-IB17800066-modify]#
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gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdOneClickRecoveryEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdWifiProfileSyncEnable|FALSE
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!if gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdOneClickRecoveryEnable == TRUE
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!if (gSiPkgTokenSpaceGuid.PcdAdlLpSupport == TRUE)
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gPlatformModuleTokenSpaceGuid.PcdWifiProfileSyncEnable|TRUE
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!endif
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!endif
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gPlatformModuleTokenSpaceGuid.PcdIgdIntHookEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdAhciEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdDTbtEnable|TRUE
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#[-start-191111-IB10189001-modify]#
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#
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# Disable Intel CapsuleEnable, this featuree was owned by Insyde Kernel
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#
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gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable|FALSE
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#[-end-191111-IB10189001-modify]#
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gPlatformModuleTokenSpaceGuid.PcdResiliencyEnable|FALSE
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gPlatformModuleTokenSpaceGuid.PcdMeResiliencyEnable|FALSE
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gPlatformModuleTokenSpaceGuid.PcdI2cTouchDriverEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdPiI2cStackEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdUsb3SerialStatusCodeEnable|FALSE
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gPlatformModuleTokenSpaceGuid.PcdUserAuthenticationEnable|TRUE
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!if (gSiPkgTokenSpaceGuid.PcdAdlLpSupport == TRUE)
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gPlatformModuleTokenSpaceGuid.PcdRemotePlatformEraseSupport|TRUE
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!endif
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gPlatformModuleTokenSpaceGuid.PcdPciHotplugEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdUsbTypeCEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdVirtualKeyboardEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdEbcEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdHddPasswordEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdNetworkEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdGigUndiEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdMouseEnable|FALSE
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gPlatformModuleTokenSpaceGuid.PcdSinitAcmBinEnable|FALSE
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gPlatformModuleTokenSpaceGuid.PcdAcmProdBinEnable|FALSE
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gPlatformModuleTokenSpaceGuid.PcdScsiEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdJpgEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdSmiVariableEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdUsbEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdUsbFnEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdDnxSupportEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdPlatformCmosAccessSupport|TRUE
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gPlatformModuleTokenSpaceGuid.PcdEnableSecureErase|TRUE
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gPlatformModuleTokenSpaceGuid.PcdUnitoolEnable|TRUE
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gBoardModuleTokenSpaceGuid.PcdFFUEnable|TRUE
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#
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# Build Switch for bin files.
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#
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!if gSiPkgTokenSpaceGuid.PcdBiosGuardEnable == TRUE
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gBoardModuleTokenSpaceGuid.PcdBiosGuardBinEnable|TRUE #BiosGuardModule.bin
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!else
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gBoardModuleTokenSpaceGuid.PcdBiosGuardBinEnable|FALSE
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!endif
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gBoardModuleTokenSpaceGuid.PcdStartupAcmProdBinEnable|FALSE #StartupAcmProd.bin
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gBoardModuleTokenSpaceGuid.PcdNhltBinEnable|TRUE #NhltIcl.bin
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gPlatformModuleTokenSpaceGuid.PcdSredirBinEnable|TRUE #Sredir.bin
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gPlatformModuleTokenSpaceGuid.PcdSinitAcmBinEnable|FALSE #SinitAc.bin
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gPlatformModuleTokenSpaceGuid.PcdH8S2113Present|FALSE
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gPlatformModuleTokenSpaceGuid.PcdNat87393Present|FALSE
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gPlatformModuleTokenSpaceGuid.PcdNct677FPresent|FALSE
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#
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# Build Switch for efi files.
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#
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gBoardModuleTokenSpaceGuid.PcdRaidDriverEfiEnable|TRUE #RaidDriver.efi
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gBoardModuleTokenSpaceGuid.PcdRsteDriverEfiEnable|TRUE #SataDriverRste.efi
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gPlatformModuleTokenSpaceGuid.PcdLegacySredirBinEnable|TRUE #LegacySredir.efi
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gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdNetworkIscsiEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdNetworkVlanEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdFatEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdCryptoEnable|TRUE # Current Smbios implementation needs this
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gPlatformModuleTokenSpaceGuid.PcdLzmaEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdDxeCompressEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdVtioEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdUserIdentificationEnable|FALSE
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gPlatformModuleTokenSpaceGuid.PcdTdsEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdOpalPasswordEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdMemoryTestEnable|TRUE
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gPlatformModuleTokenSpaceGuid.PcdDgrPolicyOverride|FALSE
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!if (gPlatformModuleTokenSpaceGuid.PcdCryptoEnable == TRUE)
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gBoardModuleTokenSpaceGuid.PcdModularCryptoEnable|TRUE
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!endif
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gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdVmdEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdCpuPcieEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdThcEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPsmiEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdAdlLpSupport|FALSE
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gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdHybridStorageSupport|TRUE
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gSiPkgTokenSpaceGuid.PcdPpamEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdStatusCodeUseTraceHub|TRUE
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!endif #PcdAdvancedFeatureEnable
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!if $(TARGET) == RELEASE
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
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!else
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
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!endif
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#
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# Silicon feature settings
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#
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!if gBoardModuleTokenSpaceGuid.PcdSecurityEnable == TRUE
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gPlatformModuleTokenSpaceGuid.PcdTpmEnable|TRUE
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!endif
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#
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# SMBIOS settings
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#
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# Disabling 64 bit Smbios Entrypoint Structure and populated tables
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# Bit0 is to enable 32 bit and Bit1 is to enable 64 bit Smbios tables
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!if gSiPkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x01
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!endif
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!if gPlatformModuleTokenSpaceGuid.PcdBeepStatusCodeEnable == TRUE
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gBeepDebugFeaturePkgTokenSpaceGuid.PcdStatusCodeUseBeep|TRUE
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!else
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gBeepDebugFeaturePkgTokenSpaceGuid.PcdStatusCodeUseBeep|FALSE
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!endif
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!if gPlatformModuleTokenSpaceGuid.PcdPostCodeStatusCodeEnable == TRUE
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gPostCodeDebugFeaturePkgTokenSpaceGuid.PcdStatusCodeUsePostCode|TRUE
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!else
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gPostCodeDebugFeaturePkgTokenSpaceGuid.PcdStatusCodeUsePostCode|FALSE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
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gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
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gEfiMdeModulePkgTokenSpaceGuid.PcdEdkiiFpdtStringRecordEnableOnly|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
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!endif
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!if (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
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#
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# In FSP API mode, the PciExpressBaseAddress is not necessary DynamicEx
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#
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gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
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!endif
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# Temporary RAM Size for FSP build
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00100000
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!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
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#
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# FSP API mode will only establish separate Heap.
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#
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gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00020000
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!else
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#
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# FSP Dispatch mode will not establish separate Stack or Heap.
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#
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gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0
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!endif
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!if $(TARGET) == DEBUG
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!if gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable == TRUE
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gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
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gPlatformModuleTokenSpaceGuid.PcdStatusCodeUseSerialIoUart|TRUE
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!endif
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!endif
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!if gSiPkgTokenSpaceGuid.PcdAdlLpSupport == TRUE
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gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|0
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!endif
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#
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# FSP Binary base address will be set in FDF basing on flash map
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#
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#[-start-191111-IB10189001-remove]#
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# gino: kernel issue, we cannot follow RC
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# gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
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# gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
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#[-end-191111-IB10189001-remove]#
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!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
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## Pcd for OptionRom.
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# Image verification policy settings:
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# ALWAYS_EXECUTE 0x00000000
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# NEVER_EXECUTE 0x00000001
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# ALLOW_EXECUTE_ON_SECURITY_VIOLATION 0x00000002
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# DEFER_EXECUTE_ON_SECURITY_VIOLATION 0x00000003
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# DENY_EXECUTE_ON_SECURITY_VIOLATION 0x00000004
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# QUERY_USER_ON_SECURITY_VIOLATION 0x00000005
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gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x00000004
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gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer|{0x8A, 0xF3, 0x87, 0x6B, 0x0F, 0xD4, 0xA3, 0x90, 0x15, 0xD7, 0x40, 0xC5, 0x3A, 0x94, 0x9B, 0xF4, 0xE0, 0x58, 0x53, 0x58, 0x87, 0x89, 0x67, 0x84, 0x60, 0xAF, 0x8E, 0xB4, 0x16, 0x1F, 0x52, 0x51}
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!endif
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!if gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
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## Indicates if to shadow PEIM on S3 boot path after memory is ready.<BR><BR>
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# TRUE - Shadow PEIM on S3 boot path after memory is ready.<BR>
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# FALSE - Not shadow PEIM on S3 boot path after memory is ready.<BR>
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# @Prompt Shadow Peim On S3 Boot.
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gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
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#
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# For RS5 (1 core, 2 thread), increase page number to avoid S3 exit fail
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#
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptRuntimeTableReservePageNumber|0x4
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!endif
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!if gSiPkgTokenSpaceGuid.PcdPpamEnable == TRUE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x11A000
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!endif
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#
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# PlatformTemporaryMmioAssignmentEnd
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#
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!if gBoardModuleTokenSpaceGuid.PcdAdvancedFeatureEnable == FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0x80000000
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xC0000000
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!endif
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!if gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE
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gPlatformModuleTokenSpaceGuid.PcdPlatformMeEDebugCapsuleImageTypeIdGuid|{GUID(gFmpDevicePlatformMonolithicGuid), GUID(gFmpDevicePlatformMeGuid)}
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gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{GUID(gFmpDevicePlatformMonolithicGuid), GUID(gFmpDevicePlatformBiosGuid)}
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!endif
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#
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# Overriding this PCD to reduce the NVRAM Reclaim frequency
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#
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!if gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
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gEfiNetworkPkgTokenSpaceGuid.PcdMaxIScsiAttemptNumber|0x04
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!endif
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[PcdsFixedAtBuild.IA32]
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gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
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gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
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[PcdsFixedAtBuild.X64]
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!if gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
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# @todo the size needs to be optimized.
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# Increase the memory size to resolve S3 exit failure due to memory resource shortage
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!if $(TARGET) == DEBUG
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gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x2600000
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!else
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gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x2600000
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!endif
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!endif
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|
|
|
!if gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
|
|
gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE
|
|
!endif
|
|
|
|
|
|
# Update PcdsFeatureFlag acording to PcdsFixedAtBuild changes
|
|
[PcdsFeatureFlag]
|
|
!if gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE
|
|
gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
|
|
!else
|
|
gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
|
|
!endif
|
|
|
|
#[-start-200420-IB17800056-modify]#
|
|
# ADL PO Temporary remove
|
|
!if gBoardModuleTokenSpaceGuid.PcdAcpiDebugFeatureEnable == TRUE
|
|
# gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable|TRUE
|
|
!else
|
|
# gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable|FALSE
|
|
!endif
|
|
#[-end-200420-IB17800056-modify]#
|
|
|
|
[PcdsDynamicHii.X64.DEFAULT]
|
|
|
|
!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
|
|
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
|
|
!endif
|
|
|
|
[PcdsDynamicDefault]
|
|
#[-start-191111-IB10189001-remove]#
|
|
# gino: kernel issue, we cannot follow RC
|
|
# gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFD20000
|
|
#[-end-191111-IB10189001-remove]#
|
|
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000
|
|
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000
|
|
|
|
#[-start-201217-IB16560234-remove]#
|
|
# H2O use type PcdsFixedAtBuild
|
|
#!if $(TARGET) == DEBUG
|
|
# gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
|
|
#!else
|
|
# gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
|
|
#!endif
|
|
#[-end-201217-IB16560234-remove]#
|
|
|
|
!if gBoardModuleTokenSpaceGuid.PcdAdvancedFeatureEnable == TRUE
|
|
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0x80000000
|
|
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xC0000000
|
|
!endif
|
|
|
|
!if (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
|
|
## Specifies max supported number of Logical Processors.
|
|
# @Prompt Configure max supported number of Logical Processorss
|
|
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
|
|
|
|
## Specifies the AP wait loop state during POST phase.
|
|
# The value is defined as below.
|
|
# 1: Place AP in the Hlt-Loop state.
|
|
# 2: Place AP in the Mwait-Loop state.
|
|
# 3: Place AP in the Run-Loop state.
|
|
# @Prompt The AP wait loop state.
|
|
gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
|
|
|
|
## Specifies the AP target C-state for Mwait during POST phase.
|
|
# The default value 0 means C1 state.
|
|
# The value is defined as below.<BR><BR>
|
|
# @Prompt The specified AP target C-state for Mwait.
|
|
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
|
|
|
|
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
|
|
!endif
|
|
|
|
!if gBoardModuleTokenSpaceGuid.PcdS4Enable == FALSE
|
|
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
|
|
!else
|
|
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE
|
|
!endif
|
|
|
|
!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
|
|
gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
|
|
|
|
gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0xFFFFFFFF
|
|
gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F
|
|
|
|
gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1
|
|
gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0
|
|
gEfiSecurityPkgTokenSpaceGuid.PcdTpm2ScrtmPolicy|1
|
|
|
|
gBoardModuleTokenSpaceGuid.PcdTpm2HierarchyChangeAuthPlatform|1
|
|
gBoardModuleTokenSpaceGuid.PcdTpm2HierarchyControlPlatform|1
|
|
gBoardModuleTokenSpaceGuid.PcdTpm2HierarchyControlEndorsement|1
|
|
gBoardModuleTokenSpaceGuid.PcdTpm2HierarchyControlOwner|1
|
|
gBoardModuleTokenSpaceGuid.PcdTpm2ChangeEps|0
|
|
gBoardModuleTokenSpaceGuid.PcdTpm2ChangePps|0
|
|
gBoardModuleTokenSpaceGuid.PcdTpm2Clear|0
|
|
|
|
!if gSiPkgTokenSpaceGuid.PcdTxtEnable == TRUE
|
|
## The PCD is used to specify if Tcg2Platform module supports TXT provision.
|
|
gBoardModuleTokenSpaceGuid.PcdTpm2TxtProvisionSupport|TRUE
|
|
!endif
|
|
|
|
!endif
|
|
|
|
!if gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
|
|
gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
|
|
gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1
|
|
!endif
|
|
|
|
!if gPlatformModuleTokenSpaceGuid.PcdOneClickRecoveryEnable == TRUE
|
|
## This value is used to configure the request and response timeout when getting the recovery image from
|
|
# remote source. The value of 5000 will be the default 5 second timeout value
|
|
# @Prompt HTTP Boot OS Image Request and Response Timeout
|
|
gEfiNetworkPkgTokenSpaceGuid.PcdHttpIoTimeout|5000
|
|
!endif
|
|
|
|
[PcdsDynamicExDefault]
|
|
|
|
!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0
|
|
#
|
|
# Include FSP PCD settings.
|
|
#
|
|
!include $(PLATFORM_FSP_BIN_PACKAGE)/FspPkgPcdShare.dsc
|
|
!endif
|
|
|
|
#[-start-191111-IB10189001-remove]#
|
|
# gino: kernel issue, we cannot follow RC
|
|
#
|
|
# FSP Binary base address will be set in FDF basing on flash map
|
|
#
|
|
# gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
|
|
#[-end-191111-IB10189001-remove]#
|
|
|
|
#[-start-201207-IB10181021-remove]#
|
|
# Move this line to Project.dsc for the customer use
|
|
# !include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/AllStructPCD.dsc
|
|
#[-end-201207-IB10181021-remove]#
|