465 lines
12 KiB
C
465 lines
12 KiB
C
/** @file
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Header file for DccProgramLib.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _DCC_PROGRAM_H_
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#define _DCC_PROGRAM_H_
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#pragma pack(1)
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typedef union {
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struct {
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//
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// Recovery mode when watchdog timer reaches the end
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// of the period without being reset.
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// 0x0: soft recovery, assert SFTRST# and maintain its
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// output frequency
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// 0x1: hard recovery, assert HRDRST# and immediately
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// revert to either the previous frequency or the
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// programmed revert frequency based on revert_mode.
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//
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UINT8 RecoverMode : 1;
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//
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// When the watchdog timer reaches the end of the
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// period without being reset, and recover_mode is set to 1:
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// 0x0: the output frequency reverts to the starting
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// frequency of the last over-clock ramp
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// 0x1: the output frequency of FOD0 and FOD1 reverts
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// according to the FOD divide ratio programmed in
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// oc_hrdrst_int and oc_hrdrst_frac.
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//
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UINT8 RevertMode : 1;
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//
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// A 0 to 1 transition will generate a reset pulse on the SFTRST# pin.
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//
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UINT8 SftrstReg : 1;
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//
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// A 0 to 1 transition will generate a reset pulse on the HRDRST# pin.
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//
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UINT8 HrdrstReq : 1;
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//
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// Sets the reset pulse width.
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// 0x0: 150 msec
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// 0x1: 300 msec
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// 0x2: 600 msec
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// 0x3: 1200 msec
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//
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UINT8 OcRstPulse : 2;
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//
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// Selects pin or CSR triggering of over-clocking frequency transitions.
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//
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UINT8 OcTrigMode : 1;
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//
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// Selects the FOD controlled by the OC engine.
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//
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UINT8 OcFodSel : 1;
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} Bits;
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UINT8 Uint8;
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} REGISTER_2C0H;
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typedef union {
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struct {
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//
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// Set over-clocking mode. This bit must not be changed
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// while a frequency transition is in progress.
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// 0x0: SFT mode
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// 0x1: Target mode
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//
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UINT8 OcMode : 1;
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//
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// Enable/disable the over-clocking block. This bit must
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// not be cleared while a frequency transition is in progress.
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// 0x0: disable
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// 0x1: enable
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//
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UINT8 OcEnable : 1;
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//
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// Selects whether the watchdog timer is restarted after
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// the first expiry. On the first expiry, it always triggers a
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// reset according to recover_mode and revert_mode.
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// 0x0: The watchdog timer stops running after it expires.
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// 0x1: The watchdog timer is restarted after it first expires.
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//
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UINT8 WdtDouble : 1;
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//
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// Reserved.
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//
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UINT8 Rsvd : 5;
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} Bits;
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UINT8 Uint8;
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} REGISTER_2C1H;
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typedef union {
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struct {
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//
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// Trigger ramp up in all oc modes when oc_trig_mode
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// selects register control. In Target mode, set this bit if
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// the target divide ratio is smaller (faster) than the
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// current divide ratio.
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//
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UINT8 OcIncr : 1;
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//
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// Trigger ramp down in all oc modes when oc_trig_mode
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// selects register control. In Target mode, set this bit if
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// the target divide ratio is larger (slower) than the current
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// divide ratio.
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//
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UINT8 OcDecr : 1;
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//
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// When this bit is written to 1,oc_target_int and
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// oc_target_frac are updated according to
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// oc_shadow_sel.
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//
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UINT8 OcCopyShadow : 1;
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//
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// Reserved.
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//
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UINT8 Rsvd3 : 1;
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//
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// Selects the OC shadow divider setting to copy to
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// oc_target_int and oc_target_frac when oc_copy_shadow is triggered.
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// 0x0: oc_shadow0_int ,oc_shadow0_frac
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// 0x1: oc_shadow1_int ,oc_shadow1_frac
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// 0x2: oc_hrdrst_int ,oc_hrdrst_frac
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// 0x3: reserved
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UINT8 OcShadowSel : 2;
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//
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// Reserved.
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//
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UINT8 Rsvd67 : 2;
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} Bits;
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UINT8 Uint8;
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} REGISTER_2CCH;
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typedef union {
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struct {
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//
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// OUTx and/or OUTxb Driver disable
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// 0x0 = OUTx and/or OUTxb Driver is enabled if not disabled by other means
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// 0x1 = OUTx and/or OUTxb Driver is disabled
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//
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UINT8 OutDis : 1;
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//
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// OUT Driver disabled state
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// Controls the state of OUTx / OUTxb when the output driver is
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// disabled.
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//
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UINT8 OutDisState : 2;
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//
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// Output Driver OE Group Select and Global Output Enable Exclusion
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// Sets which OE group this driver is in, and if not assigned to a group,
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// can also exclude global output enables from applying to the clock.
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//
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UINT8 OutDisGroup : 3;
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//
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// Output Driver OE Mode
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// Controls whether the output enable acts synchronously or
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// asynchronously with respect to the output divider clock. Must be set to
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// asynchronous mode when outputting SYSREF.
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//
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UINT8 OutOeMode : 1;
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//
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// Output Driver Power Down
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// Powers down the output clock driver.
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// 0x0 = output driver is powered up
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// 0x1 = output driver is powered down
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//
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UINT8 OutPd : 1;
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} Bits;
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UINT8 Uint8;
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} REGISTER_ODRV_EN;
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typedef union {
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//
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// The RC260X provide 9 bits to apply integer settings.
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//
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struct {
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UINT8 Byte0 : 8;
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UINT8 Byte1 : 1;
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UINT8 Rsvd : 7;
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} Parts;
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UINT16 Uint16;
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} REGISTER_INTEGER;
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typedef union {
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//
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// The RC260X provide 28 bits to apply fraction settings.
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//
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struct {
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UINT8 Byte0 : 8;
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UINT8 Byte1 : 8;
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UINT8 Byte2 : 8;
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UINT8 Byte3 : 4;
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UINT8 Rsvd : 4;
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} Parts;
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UINT32 Uint32;
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} REGISTER_FRACTIONAL;
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#pragma pack()
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#define CPU_BCLK_OC_FOD 0
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#define PEG_DMI_CLK_FOD 1
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#define RENESAS_260X_1B_MODE_SET_PAGE_CMD 0xFD
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#define RENESAS_260X_ADDRESS 0x09
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#define RENESAS_260X_CHIP_FREQUENCY 10000 // 10Ghz = 10000Mhz
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#define RENESAS_260X_OUTPUT_DISABLE BIT0
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/**
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Set register page address.
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@param[in] Page Page address of the register.
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@retval Status
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**/
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EFI_STATUS
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DccRc260xSetPage (
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IN UINT8 Page
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);
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/**
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Read data from RC260X register.
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@param[in] Register Register address
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@retval Data Data read from RC260X register.
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**/
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UINT8
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DccRegisterValueRead (
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IN UINT8 Register
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);
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/**
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Write data to RC260X register.
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@param[in] Register Register address
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@param[in] Data Data that will be set.
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**/
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VOID
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DccRegisterValueWrite (
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IN UINT8 Register,
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IN UINT8 Data
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);
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/**
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Set divider value to shadow register0.
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@param[in] Integer The integer parts of divider register.
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@param[in] Fractional The fractional parts of divider register.
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**/
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VOID
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SetDividerValueToShadowReg0 (
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IN REGISTER_INTEGER Integer,
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IN REGISTER_FRACTIONAL Fractional
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);
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/**
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Set divider value to shadow register1.
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@param[in] Integer The integer parts of divider register.
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@param[in] Fractional The fractional parts of divider register.
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**/
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VOID
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SetDividerValueToShadowReg1 (
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IN REGISTER_INTEGER Integer,
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IN REGISTER_FRACTIONAL Fractional
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);
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/**
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Apply current divider settings to a register.
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@param[in] OcFodSelect Choose Fractional Output Divider that will be set.
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@param[in] Integer The integer parts of divider register.
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@param[in] Fractional The fractional parts of divider register.
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**/
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VOID
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ApplyDividerValue (
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IN UINT8 OcFodSelect,
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IN REGISTER_INTEGER Integer,
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IN REGISTER_FRACTIONAL Fractional
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);
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/**
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Set divider value to divider register.
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@param[in] Integer The integer parts of divider register.
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@param[in] Fractional The fractional parts of divider register.
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**/
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VOID
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SetDivider (
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IN REGISTER_INTEGER Integer,
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IN REGISTER_FRACTIONAL Fractional
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);
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/**
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Get original divider setting from the shadow register0
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@param[in, out] Integer The integer parts of divider register.
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@param[in, out] Fractional The fractional parts of divider register.
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**/
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VOID
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GetCurrentDividerSettingsFromShadowReg0 (
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IN REGISTER_INTEGER *Integer,
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IN REGISTER_FRACTIONAL *Fractional
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);
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/**
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Get original divider setting from the shadow register1
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@param[in, out] Integer The integer parts of divider register.
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@param[in, out] Fractional The fractional parts of divider register.
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**/
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VOID
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GetCurrentDividerSettingsFromShadowReg1 (
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IN REGISTER_INTEGER *Integer,
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IN REGISTER_FRACTIONAL *Fractional
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);
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/**
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Get original divider setting from a register.
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@param[in] OcFodSelect Choose Fractional Output Divider that will be read.
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@param[in, out] Integer The integer parts of divider register.
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@param[in, out] Fractional The fractional parts of divider register.
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**/
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VOID
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GetCurrentDividerSettings (
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IN UINT8 OcFodSelect,
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IN REGISTER_INTEGER *Integer,
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IN REGISTER_FRACTIONAL *Fractional
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);
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/**
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Calculate the divider value that will be set.
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DividerFreq = ChipFreq / TargetFreq.
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@param[in] TargetFreq Frequency of the target device that will be set.
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@param[in, out] Integer The integer parts of divider register.
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@param[in, out] Fractional The fractional parts of divider register.
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**/
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VOID
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GetNextDividerSettings (
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IN UINT16 TargetFreq,
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IN REGISTER_INTEGER *Integer,
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IN REGISTER_FRACTIONAL *Fractional
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);
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/**
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Program chip to adjust clock frequencey for target device.
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@param[in] OcFodSelect Choose Fractional Output Divider which will be modified.
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@param[in] TargetFreq Frequency of the target device that will be set.
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**/
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VOID
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ProgramBclkFreq (
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IN UINT8 OcFodSelect,
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IN UINT16 TargetFreq
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);
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/**
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Program Dcc chip for Cpu Bclk
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@param[in] TargetFreq Frequency of the target device that will be set.
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**/
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VOID
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ProgramCpuBclkFreq (
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IN UINT16 TargetFreq
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);
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/**
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Program Dcc chip for Peg/Dmi Clk
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@param[in] TargetFreq Frequency of the target device that will be set.
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**/
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VOID
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ProgramPegDmiClkFreq (
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IN UINT16 TargetFreq
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);
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/**
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Check if Renesas RC260X exist or not.
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**/
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BOOLEAN
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CheckDccClkChipExist (
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VOID
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);
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/**
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Disable Output Clock on all Out[X]/Out[X]b
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**/
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VOID
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DisableExternalClockOutput (
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VOID
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);
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/**
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Enable Output Clock on all Out[X]/Out[X]b
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**/
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VOID
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EnableExternalClockOutput (
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VOID
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);
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#endif
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