106 lines
4.7 KiB
C
106 lines
4.7 KiB
C
/** @file
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include "Uefi.h"
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CHAR16 *mBoardIdIndex[] = {
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//L"0123456789ABCDEF0123456789ABCDEF", // !! Do not exceed 32 characters !!
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L"TBD", // 0x00
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L"AlderLake-M LP4x RVP", // 0x01
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L"AlderLake-M LP5 RVP", // 0x02
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L"AlderLake-M LP5 PMIC RVP", // 0x03
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L"TBD", // 0x04
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L"TBD", // 0x05
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L"TBD", // 0x06
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L"TBD", // 0x07
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L"TBD", // 0x08
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L"TBD", // 0x09
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L"TBD", // 0x0A
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L"TBD", // 0x0B
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L"TBD", // 0x0C
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L"TBD", // 0x0D
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L"TBD", // 0x0E
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L"AlderLake-M LP5x AEP", // 0x0F
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L"AlderLake-P LP4x RVP", // 0x10
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L"TBD", // 0x11
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L"AlderLake-P DDR5 RVP", // 0x12
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L"AlderLake-P LP5 RVP", // 0x13
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L"AlderLake-P DDR4 RVP", // 0x14
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L"TBD", // 0x15
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L"TBD", // 0x16
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L"TBD", // 0x17
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L"TBD", // 0x18
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L"TBD", // 0x19
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L"TBD", // 0x1A
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L"TBD", // 0x1B
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L"TBD", // 0x1C
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L"TBD", // 0x1D
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L"TBD", // 0x1E
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L"TBD", // 0x1F
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L"AlderLake-S TGP-H DDR4 ERB2", // 0x20
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L"AlderLake-S TGP-H DDR4 CRB", // 0x21
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L"AlderLake-S TGP-H DDR4 CRB PPV", // 0x22
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L"TBD", // 0x23
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L"AlderLake-S TGP-H DDR5 CRB", // 0x24
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L"TBD", // 0x25
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L"ADL-S ADP-S DDR4 UDIMM ERB1", // 0x26
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L"AlderLake-S ADP-S DDR4 UDIMM CRB", // 0x27
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L"ADL-S ADP-S DDR4 UDIMM CRB EV", // 0x28
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L"ADL-S ADP-S DDR4 UDIMM CRB CPV", // 0x29
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L"TBD", // 0x2A
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L"AlderLake-S ADP-S DDR5 UDIMM CRB", // 0x2B
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L"ADL-S ADP-S DDR5 UDIMM CRB PPV", // 0x2C
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L"TBD", // 0x2D
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L"ADL-S ADP-S DDR5 UDIMM 2DPC CRB", // 0x2E
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L"TBD", // 0x2F
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L"ADL-S ADP-S DDR5 SODIMM CRB", // 0x30
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L"TBD", // 0x31
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L"ADL-S HSIO UDIMM DDR4 2DPC RVP", // 0x32
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L"AlderLake S ADP-S DDR5 AEP", // 0x33
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L"ADL-S ADP-S DDR5 Single Rail CRB", // 0x34
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L"ADL-S ADP-S DDR4 SODIMM CRB", // 0x35
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L"ADL-S ADP-S DDR5 UDIMM OC CRB", // 0x36
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L"TBD", // 0x37
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L"TBD", // 0x38
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L"TBD", // 0x39
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L"AlderLake-S SBGA DDR5 SODIMM ERB", // 0x3A
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L"AlderLake-S SBGA DDR5 SODIMM CRB", // 0x3B
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L"AlderLake-S SBGA DDR5 SODIMM PPV", // 0x3C
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L"TBD", // 0x3D
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L"AlderLake-S SBGA DDR4 SODIMM CRB", // 0x3E
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L"AlderLake-P Simics Board" // 0x3F
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};
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UINT8 mSizeOfmBoardIndex = sizeof(mBoardIdIndex)/sizeof(CHAR16*);
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