483 lines
20 KiB
C
483 lines
20 KiB
C
/** @file
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Intel PEI TBT Policy update by board configuration
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2017 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include "PeiPolicyBoardConfig.h"
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#include <Ppi/PeiDTbtPolicy.h>
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#include <PlatformBoardId.h>
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#include <Library/PmcLib.h>
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#include <Pins/GpioPinsVer2Lp.h>
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#include <Pins/GpioPinsVer2H.h>
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#include <Pins/GpioPinsVer4S.h>
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#include <Library/GpioLib.h>
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#include <Ppi/ReadOnlyVariable2.h>
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#include <Library/PcdLib.h>
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#include <Library/CpuPlatformLib.h>
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#include <TcssDataHob.h>
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/**
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Configure dTBT Force Power pin for debug mode.
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**/
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VOID
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DTbtForcePwrGpioPreMem (
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VOID
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)
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{
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GPIO_CONFIG GpioConfig;
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GPIO_PAD GpioPad[2] = {0};
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EFI_STATUS Status;
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SETUP_DATA SetupData;
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UINTN VarSize;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
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UINT8 Index;
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DEBUG ((DEBUG_INFO, "DTbtForcePwrGpioPreMem Start\n"));
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//
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// Locate Setup variables
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//
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Status = PeiServicesLocatePpi (
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&gEfiPeiReadOnlyVariable2PpiGuid,
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0,
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NULL,
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(VOID **) &VariableServices
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi failed\n"));
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return;
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}
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VarSize = sizeof (SETUP_DATA);
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Status = VariableServices->GetVariable (
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VariableServices,
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L"Setup",
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&gSetupVariableGuid,
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NULL,
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&VarSize,
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&SetupData
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "GetVariable (SetupData) failed\n"));
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return;
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}
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for (Index = 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) {
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if (Index == 0) {
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if (PcdGet32 (PcdBoarddTBTForcePwrGpio0)) {
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GpioPad[Index] = PcdGet32 (PcdBoarddTBTForcePwrGpio0);
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}
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} else {
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if (PcdGet32 (PcdBoarddTBTForcePwrGpio1)) {
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GpioPad[Index] = PcdGet32 (PcdBoarddTBTForcePwrGpio1);
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}
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}
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if (GpioPad[Index] != 0) {
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GpioGetPadConfig (GpioPad[Index], &GpioConfig);
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if ((SetupData.Gpio3ForcePwr == 1) && (SetupData.DTbtController[Index]==1)) {
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//
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// value 1: Set the GPIO pin to high active (debug mode)
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// value 0: default
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//
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GpioConfig.OutputState = GpioOutHigh;
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DEBUG ((DEBUG_INFO, "Set FP Pin\n"));
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} else {
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GpioConfig.OutputState = GpioOutLow;
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DEBUG ((DEBUG_INFO, "Clear FP Pin\n"));
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}
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GpioSetPadConfig (GpioPad[Index], &GpioConfig);
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DEBUG ((DEBUG_INFO, "dTBT Force Power Gpio for controller %d is : 0x%08x\n",Index, GpioPad[Index]));
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}
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}
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DEBUG ((DEBUG_INFO, "DTbtForcePwrGpioPreMem End\n"));
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}
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/**
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Configure dTBT RTD Power pin for debug mode.
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**/
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VOID
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DTbtRTD3PwrGpioPreMem (
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VOID
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)
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{
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GPIO_CONFIG GpioConfig;
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GPIO_PAD GpioPad[MAX_DTBT_CONTROLLER_NUMBER];
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EFI_STATUS Status;
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SETUP_DATA SetupData;
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UINTN VarSize;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
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UINT8 Index;
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DEBUG ((DEBUG_INFO, "DTbtRTD3PwrGpioPreMem Start\n"));
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ZeroMem(GpioPad, MAX_DTBT_CONTROLLER_NUMBER);
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//
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// Locate Setup variables
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//
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Status = PeiServicesLocatePpi (
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&gEfiPeiReadOnlyVariable2PpiGuid,
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0,
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NULL,
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(VOID **) &VariableServices
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi failed\n"));
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return;
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}
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VarSize = sizeof (SETUP_DATA);
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Status = VariableServices->GetVariable (
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VariableServices,
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L"Setup",
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&gSetupVariableGuid,
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NULL,
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&VarSize,
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&SetupData
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "GetVariable (SetupData) failed\n"));
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return;
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}
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//
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// To get the DTBT GPIO setting of DTBT Controll 0 / 1
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// Set the OutputState to GpioOutLow prevents the device show in device manager when the DTBT disable or
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// disable of DTBT Controll 0 / 1
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//
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for (Index = 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) {
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if ((SetupData.DiscreteTbtSupport == 0) || (SetupData.DTbtController[Index] == 0)) {
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switch (Index) {
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case 0:
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GpioPad[Index] = PcdGet32 (PcdBoarddTBTRTD3PwrGpio0);
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break;
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case 1:
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GpioPad[Index] = PcdGet32 (PcdBoarddTBTRTD3PwrGpio1);
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break;
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default:
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GpioPad[Index] = 0;
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break;
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}
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if (GpioPad[Index] != 0) {
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GpioGetPadConfig (GpioPad[Index], &GpioConfig);
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GpioConfig.OutputState = GpioOutLow;
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GpioSetPadConfig (GpioPad[Index], &GpioConfig);
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DEBUG ((DEBUG_INFO, "DTBT RTD3 Gpio for controller %d is : 0x%08x\n",Index, GpioPad[Index]));
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}
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}
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}
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DEBUG ((DEBUG_INFO, "DTbtRTD3PwrGpioPreMem End\n"));
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}
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/**
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Configure Discrete DpMux Init PreMeme.
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**/
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VOID
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DiscreteDpMuxInitPreMem (
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VOID
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)
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{
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GPIO_CONFIG GpioConfig;
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GPIO_PAD GpioPad;
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EFI_STATUS Status;
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SETUP_DATA SetupData;
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UINTN VarSize;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
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DEBUG ((DEBUG_INFO, "DiscreteDpMuxInitPreMem Start\n"));
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GpioPad = 0; // Assign GPIO PAD Value to 0.
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VarSize = 0;
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//
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// Locate Setup variables
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//
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Status = PeiServicesLocatePpi (
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&gEfiPeiReadOnlyVariable2PpiGuid,
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0,
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NULL,
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(VOID **) &VariableServices
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi failed\n"));
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return;
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}
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VarSize = sizeof (SETUP_DATA);
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Status = VariableServices->GetVariable (
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VariableServices,
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L"Setup",
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&gSetupVariableGuid,
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NULL,
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&VarSize,
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&SetupData
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "GetVariable (SetupData) failed\n"));
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return;
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}
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if (PcdGet32 (PcdDpMuxGpio)) {
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GpioPad = PcdGet32 (PcdDpMuxGpio);
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GpioGetPadConfig (GpioPad, &GpioConfig);
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if (SetupData.DpInExternalEn == 1) {
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//
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// value 1: Set the GPIO pin to high active
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// value 0: default
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//
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GpioConfig.OutputState = GpioOutHigh;
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DEBUG ((DEBUG_INFO, "Enable DP Mux switch\n"));
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} else {
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GpioConfig.OutputState = GpioOutLow;
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DEBUG ((DEBUG_INFO, "Disable DP Mux switch\n"));
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}
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GpioSetPadConfig (GpioPad, &GpioConfig);
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DEBUG ((DEBUG_INFO, "Discrete DP Mux is : 0x%08x\n", GpioPad));
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} else {
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DEBUG ((DEBUG_ERROR, "PcdDpMuxGpio is NULL : %d\n", PcdGet32 (PcdDpMuxGpio)));
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}
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DEBUG ((DEBUG_INFO, "DiscreteDpMuxInitPreMem End\n"));
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}
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/**
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This function performs PEI TBT Policy update by board configuration.
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@retval EFI_SUCCESS The SI Policy is successfully updated.
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@retval Others The SI Policy is not successfully updated.
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**/
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EFI_STATUS
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EFIAPI
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UpdatePeiTbtPolicyBoardConfig (
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VOID
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)
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{
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#if FixedPcdGetBool (PcdDTbtEnable) == 1
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EFI_STATUS Status;
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PEI_DTBT_POLICY *PeiDTbtConfig;
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UINT16 BoardId;
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DEBUG ((DEBUG_INFO, "Updating TBT Policy by board config in Post-Mem\n"));
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Status = EFI_SUCCESS;
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PeiDTbtConfig = NULL;
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PcdSet32S (PcdBoarddTBTForcePwrGpio0, 0); //Initization
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PcdSet32S (PcdBoarddTBTForcePwrGpio1, 0); //Initization
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PcdSet32S (PcdBoarddTBTRTD3PwrGpio0, 0); //Initization
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PcdSet32S (PcdBoarddTBTRTD3PwrGpio1, 0); //Initization
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//
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// Ascertain BoardId
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//
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BoardId = PcdGet16 (PcdBoardId);
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DEBUG ((DEBUG_INFO, "UpdatePeiDTbtConfigBoardConfig - BoardId is 0x%04X\n", BoardId));
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Status = PeiServicesLocatePpi (
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&gPeiDTbtPolicyPpiGuid,
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0,
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NULL,
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(VOID **) &PeiDTbtConfig
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);
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if (PeiDTbtConfig != NULL) {
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//
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// Update TBT Config Block based on BoardId value.
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//
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switch (BoardId) {
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case BoardIdAdlSAdpSDdr4UDimm2DCrbEv:
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case BoardIdAdlSAdpSDdr4UDimm2DCrbCpv:
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case BoardIdAdlSAdpSDdr4UDimm2DCrb:
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case BoardIdAdlSAdpSDdr5UDimm1DCrb:
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case BoardIdAdlSAdpSDdr5UDimm2DCrb:
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case BoardIdAdlSAdpSDdr5UDimm1DCrbPpv:
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case BoardIdAdlSAdpSDdr5UDimm1DSr:
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DEBUG ((DEBUG_INFO, "Update DTBT Platform Specific Details...\n"));
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PcdSet32S (PcdBoarddTBTForcePwrGpio0, GPIO_VER4_S_GPP_G0); //1: Set the GPIO pin to high active (debug mode); 0: default
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PeiDTbtConfig->DTbtControllerConfig[0].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRpNumber = 9; //Connected to RP 09
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.GpioPad = GPIO_VER4_S_GPP_G7;
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioPad = 0;
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioLevel = 0;
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PeiDTbtConfig->DTbtGenericConfig.DTbtSharedGpioConfiguration = TRUE;
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PeiDTbtConfig->DTbtGenericConfig.PcieRstSupport = FALSE;
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if (GpioCheckFor2Tier (GPIO_VER4_S_GPP_G7)) {
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32 ('X', 'T', 'B', 'T');
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignaturePorting = 0;
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}
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break;
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case BoardIdAdlSAdpSDdr5SODimmCrb:
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case BoardIdAdlSAdpSDdr4SODimmCrb:
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DEBUG((DEBUG_INFO, "Update DTBT Platform Specific Details...\n"));
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PcdSet32S (PcdBoarddTBTForcePwrGpio0, GPIO_VER4_S_GPP_G0); //1: Set the GPIO pin to high active (debug mode); 0: default
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PeiDTbtConfig->DTbtControllerConfig[0].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRpNumber = 25; //Connected to RP 25
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.GpioPad = GPIO_VER4_S_GPP_G7;
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioPad = 0;
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioLevel = 0;
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PeiDTbtConfig->DTbtGenericConfig.DTbtSharedGpioConfiguration = TRUE;
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PeiDTbtConfig->DTbtGenericConfig.PcieRstSupport = FALSE;
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if (GpioCheckFor2Tier (GPIO_VER4_S_GPP_G7)) {
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32 ('X', 'T', 'B', 'T');
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignaturePorting = 0;
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}
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break;
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case BoardIdAdlSAdpSDdr5UDimm1DAep:
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DEBUG ((DEBUG_INFO, "Update DTBT Platform Specific Details for AEP...\n"));
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PcdSet32S (PcdBoarddTBTForcePwrGpio0, (UINTN) GPIO_VER4_S_GPP_G0); //1: Set the GPIO pin to high active (debug mode); 0: default
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PeiDTbtConfig->DTbtControllerConfig[0].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRpNumber = 21; //Connected to RP 21
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.GpioPad = GPIO_VER4_S_GPP_G7;
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioPad = 0;
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioLevel = 0;
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PeiDTbtConfig->DTbtGenericConfig.DTbtSharedGpioConfiguration = FALSE;
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PeiDTbtConfig->DTbtGenericConfig.PcieRstSupport = FALSE;
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if (GpioCheckFor2Tier(GPIO_VER4_S_GPP_G7)) {
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32('X', 'T', 'B', 'T');
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignaturePorting = 0;
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}
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PcdSet32S (PcdBoarddTBTForcePwrGpio1, (UINTN) GPIO_VER4_S_GPP_D13); //1: Set the GPIO pin to high active (debug mode); 0: default
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PeiDTbtConfig->DTbtControllerConfig[1].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
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PeiDTbtConfig->DTbtControllerConfig[1].PcieRpNumber = 25; //Connected to RP 25
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PeiDTbtConfig->DTbtControllerConfig[1].CioPlugEventGpio.GpioPad = GPIO_VER4_S_GPP_D14;
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PeiDTbtConfig->DTbtControllerConfig[1].PcieRstGpio.GpioPad = 0;
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PeiDTbtConfig->DTbtControllerConfig[1].PcieRstGpio.GpioLevel = 0;
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if (GpioCheckFor2Tier(GPIO_VER4_S_GPP_D14)) {
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PeiDTbtConfig->DTbtControllerConfig[1].CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32('X', 'T', 'B', 'T');
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PeiDTbtConfig->DTbtControllerConfig[1].CioPlugEventGpio.AcpiGpeSignaturePorting = 0;
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}
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break;
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case BoardIdAdlSAdpSSbgaDdr5SODimmErb:
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case BoardIdAdlSAdpSSbgaDdr5SODimmCrb:
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DEBUG ((DEBUG_INFO, "Update DTBT Platform Specific Details for SBGA DDR5...\n"));
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PcdSet32S (PcdBoarddTBTForcePwrGpio0, (UINTN) GPIO_VER4_S_GPP_G0); //1: Set the GPIO pin to high active (debug mode); 0: default
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PeiDTbtConfig->DTbtControllerConfig[0].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRpNumber = 25; //Connected to RP 25
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.GpioPad = GPIO_VER4_S_GPP_G7;
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioPad = GPIO_VER4_S_GPP_F16;
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PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioLevel = 0;
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PeiDTbtConfig->DTbtGenericConfig.DTbtSharedGpioConfiguration = FALSE;
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PeiDTbtConfig->DTbtGenericConfig.PcieRstSupport = TRUE;
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if (GpioCheckFor2Tier(GPIO_VER4_S_GPP_G7)) {
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32('X', 'T', 'B', 'T');
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PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignaturePorting = 0;
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}
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PcdSet32S (PcdBoarddTBTForcePwrGpio1, (UINTN) GPIO_VER4_S_GPP_G0); //1: Set the GPIO pin to high active (debug mode); 0: default
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PeiDTbtConfig->DTbtControllerConfig[1].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
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PeiDTbtConfig->DTbtControllerConfig[1].PcieRpNumber = 9; //Connected to RP 9
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PeiDTbtConfig->DTbtControllerConfig[1].CioPlugEventGpio.GpioPad = GPIO_VER4_S_GPP_B22;
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PeiDTbtConfig->DTbtControllerConfig[1].PcieRstGpio.GpioPad = GPIO_VER4_S_GPP_F2;
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PeiDTbtConfig->DTbtControllerConfig[1].PcieRstGpio.GpioLevel = 0;
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if (GpioCheckFor2Tier(GPIO_VER4_S_GPP_B22)) {
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PeiDTbtConfig->DTbtControllerConfig[1].CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32('X', 'T', 'B', 'T');
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PeiDTbtConfig->DTbtControllerConfig[1].CioPlugEventGpio.AcpiGpeSignaturePorting = 0;
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}
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break;
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case BoardIdAdlSAdpSSbgaDdr5SODimmAep:
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DEBUG ((DEBUG_INFO, "Update DTBT Platform Specific Details for SBGA DDR5 AEP...\n"));
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PcdSet32S (PcdBoarddTBTForcePwrGpio0, (UINTN) GPIO_VER4_S_GPP_G0); //1: Set the GPIO pin to high active (debug mode); 0: default
|
|
PeiDTbtConfig->DTbtControllerConfig[0].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
|
|
PeiDTbtConfig->DTbtControllerConfig[0].PcieRpNumber = 9; //Connected to RP 9
|
|
PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.GpioPad = GPIO_VER4_S_GPP_G7;
|
|
PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioPad = GPIO_VER4_S_GPP_F16;
|
|
PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioLevel = 0;
|
|
PeiDTbtConfig->DTbtGenericConfig.DTbtSharedGpioConfiguration = 0;
|
|
PeiDTbtConfig->DTbtGenericConfig.PcieRstSupport = 0;
|
|
if (GpioCheckFor2Tier(GPIO_VER4_S_GPP_G7)) {
|
|
PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32('X', 'T', 'B', 'T');
|
|
PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignaturePorting = 0;
|
|
}
|
|
break;
|
|
case BoardIdAdlSAdpSSbgaDdr4SODimmCrb:
|
|
DEBUG ((DEBUG_INFO, "Update DTBT Platform Specific Details for SBGA DDR4...\n"));
|
|
PcdSet32S (PcdBoarddTBTForcePwrGpio0, (UINTN) GPIO_VER4_S_GPP_G0); //1: Set the GPIO pin to high active (debug mode); 0: default
|
|
PcdSet32S (PcdBoarddTBTRTD3PwrGpio0, (UINTN) GPIO_VER4_S_GPP_F5);
|
|
PeiDTbtConfig->DTbtControllerConfig[0].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
|
|
PeiDTbtConfig->DTbtControllerConfig[0].PcieRpNumber = 25; //Connected to RP 25
|
|
PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.GpioPad = GPIO_VER4_S_GPP_G7;
|
|
PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioPad = GPIO_VER4_S_GPP_F16;
|
|
PeiDTbtConfig->DTbtControllerConfig[0].PcieRstGpio.GpioLevel = 0;
|
|
PeiDTbtConfig->DTbtGenericConfig.DTbtSharedGpioConfiguration = FALSE;
|
|
PeiDTbtConfig->DTbtGenericConfig.PcieRstSupport = TRUE;
|
|
if (GpioCheckFor2Tier(GPIO_VER4_S_GPP_G7)) {
|
|
PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32('X', 'T', 'B', 'T');
|
|
PeiDTbtConfig->DTbtControllerConfig[0].CioPlugEventGpio.AcpiGpeSignaturePorting = 0;
|
|
}
|
|
DTbtRTD3PwrGpioPreMem ();
|
|
break;
|
|
case BoardIdAdlPDdr5MRRvp:
|
|
DEBUG((DEBUG_INFO, "Update DTBT Platform Specific Details for ADL-P DDR5 2 DTBT MR Controller Configuration...\n"));
|
|
PcdSet32S (PcdBoarddTBTForcePwrGpio0, (UINTN) GPIO_VER2_LP_GPP_D12); //1: Set the GPIO pin to high active (debug mode); 0: default
|
|
PeiDTbtConfig->DTbtControllerConfig[0].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
|
|
PeiDTbtConfig->DTbtControllerConfig[0].PcieRpNumber = 5; //Connected to RP 5-8
|
|
|
|
PcdSet32S (PcdBoarddTBTForcePwrGpio1, (UINTN) GPIO_VER2_LP_GPP_D12); //1: Set the GPIO pin to high active (debug mode); 0: default
|
|
PeiDTbtConfig->DTbtControllerConfig[1].Type = 0x01;// TYPE_PCIE;//DTBT_TYPE_PCH
|
|
PeiDTbtConfig->DTbtControllerConfig[1].PcieRpNumber = 9; //Connected to RP 9-12
|
|
break;
|
|
default:
|
|
DEBUG ((DEBUG_INFO, "UpdatePeiDTbtConfigBoardConfig - Unhandled BoardId 0x%04X\n", BoardId));
|
|
break;
|
|
}
|
|
|
|
//
|
|
// USB4 SW CM support setting
|
|
//
|
|
PeiDTbtConfig->DTbtGenericConfig.Usb4CmMode = USB4_CM_MODE_SWITCH_UNSUPPORTED;
|
|
DEBUG ((DEBUG_INFO, "DTBT USB4 CM mode = 0x%0x in board config init\n", PeiDTbtConfig->DTbtGenericConfig.Usb4CmMode));
|
|
} // if (PeiDTbtConfig != NULL)
|
|
|
|
//
|
|
// Discrete DP Mux Switch GPIO Setting
|
|
// The setup option will be hidden if PcdDpMuxGpio is NULL
|
|
//
|
|
switch (BoardId) {
|
|
case BoardIdAdlSAdpSSbgaDdr5SODimmErb:
|
|
case BoardIdAdlSAdpSSbgaDdr5SODimmCrb:
|
|
PcdSet32S (PcdDpMuxGpio, GPIO_VER4_S_GPP_F0);
|
|
break;
|
|
case BoardIdAdlPDdr5MRRvp:
|
|
PcdSet32S (PcdDpMuxGpio, GPIO_VER2_LP_GPP_A7);
|
|
break;
|
|
default:
|
|
DEBUG ((DEBUG_INFO, "PcdDpMuxGpio is unsupported\n"));
|
|
break;
|
|
}
|
|
DiscreteDpMuxInitPreMem ();
|
|
DTbtForcePwrGpioPreMem ();
|
|
|
|
return Status;
|
|
#else
|
|
return EFI_SUCCESS;
|
|
#endif
|
|
}
|