227 lines
5.6 KiB
Plaintext
227 lines
5.6 KiB
Plaintext
## @file
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# Alderlake S Pcie Clock configuration file.
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#
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# @copyright
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# INTEL CONFIDENTIAL
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# Copyright 2020 - 2021 Intel Corporation.
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#
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# The source code contained or described herein and all documents related to the
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# source code ("Material") are owned by Intel Corporation or its suppliers or
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# licensors. Title to the Material remains with Intel Corporation or its suppliers
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# and licensors. The Material may contain trade secrets and proprietary and
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# confidential information of Intel Corporation and its suppliers and licensors,
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# and is protected by worldwide copyright and trade secret laws and treaty
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# provisions. No part of the Material may be used, copied, reproduced, modified,
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# published, uploaded, posted, transmitted, distributed, or disclosed in any way
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# without Intel's prior express written permission.
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#
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# No license under any patent, copyright, trade secret or other intellectual
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# property right is granted to or conferred upon you by disclosure or delivery
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# of the Materials, either expressly, by implication, inducement, estoppel or
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# otherwise. Any license under such intellectual property rights must be
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# express and approved by Intel in writing.
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#
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# Unless otherwise agreed by Intel in writing, you may not remove or alter
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# this notice or any other notice embedded in Materials by Intel or
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# Intel's suppliers or licensors in any way.
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#
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# This file contains a 'Sample Driver' and is licensed as such under the terms
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# of your license agreement with Intel or your vendor. This file may be modified
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# by the user, subject to the additional terms of the license agreement.
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#
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# @par Specification
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##
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5UDimm1DAep]
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gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
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{{
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PCIE_PEG + 1, // 1x16 PEG slot
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NOT_USED,
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 6, // LAN Foxville
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 7, // M.2 Key E WLAN
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PCIE_PCH + 20, // Maple Ridge (BP)
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PCIE_PEG, // M.2 Key M PEG Slot
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PCIE_PCH + 12, // M.2 Socket3 Key M SSD 1
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PCIE_PCH + 24, // Maple Ridge (FP)
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PCIE_PCH + 8, // EDSFF Hot Swappable Ruler storage
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NOT_USED,
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NOT_USED,
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NOT_USED
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}}
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)}
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5UDimm1DCrb]
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gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
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{{
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PCIE_PEG + 1,
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NOT_USED,
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PCIE_PCH + 20, // PCIE x4 Slot 1
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NOT_USED,
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NOT_USED,
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LAN_CLOCK,
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 7, // M.2_WLAN
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PCIE_PCH, // M.2_SSD_3
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PCIE_PEG, // CPU_M.2_SSD
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PCIE_PCH + 12, // M.2_SSD
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PCIE_PCH + 24, // M.2_SSD_2
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PCIE_PCH + 8, // PCIE X4_SLOT_2
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PCIE_PCH + 4, // PCIE X2_SLOT_3
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NOT_USED,
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NOT_USED
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}}
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)}
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr4UDimm2DCrb]
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gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
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{{
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PCIE_PEG + 1,
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PCIE_PEG + 2,
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PCIE_PCH + 20, // PCIE x4 Slot 1
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NOT_USED,
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NOT_USED,
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LAN_CLOCK,
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 7, // M.2_WLAN
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PCIE_PCH, // M.2_SSD_3
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PCIE_PEG, // CPU_M.2_SSD
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PCIE_PCH + 12, // M.2_SSD
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PCIE_PCH + 24, // M.2_SSD_2
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PCIE_PCH + 8, // PCIE X4_SLOT_2
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PCIE_PCH + 4, // PCIE X2_SLOT_3
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NOT_USED,
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NOT_USED
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}}
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)}
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr4SODimmCrb]
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gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
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{{
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PCIE_PEG + 1,
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NOT_USED,
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PCIE_PCH + 20, // PCIE x4 Slot 1
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 6, // Foxville
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 7, // M.2_WLAN
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PCIE_PCH, // M.2_SSD_3
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PCIE_PEG, // CPU_M.2_SSD
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PCIE_PCH + 12, // M.2_SSD
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PCIE_PCH + 24, // Thunderbolt
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PCIE_PCH + 8, // PCIE X4_SLOT_2
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PCIE_PCH + 4, // PCIE X2_SLOT_3
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NOT_USED,
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NOT_USED
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}}
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)}
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5SODimmCrb]
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gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
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{{
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PCIE_PEG + 1,
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NOT_USED,
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PCIE_PCH + 20, // PCIE x4 Slot 1
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 6, // Foxville
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 7, // M.2_WLAN
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PCIE_PCH, // M.2_SSD_3
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PCIE_PEG, // CPU_M.2_SSD
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PCIE_PCH + 12, // M.2_SSD
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PCIE_PCH + 24, // TBT
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PCIE_PCH + 8, // PCIE X4_SLOT_2
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PCIE_PCH + 4, // PCIE X2_SLOT_3
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NOT_USED,
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NOT_USED
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}}
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)}
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr5SODimmErb]
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gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
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{{
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PCIE_PEG + 1, // x16 PEG Slot
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NOT_USED,
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PCIE_PCH + 12, // PCIE x4 Slot 1
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 6, // Foxville
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 7, // M.2_WLAN
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PCIE_PCH + 1, // M.2_WWAN
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PCIE_PEG, // CPU_M.2 Key M
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PCIE_PCH + 20, // M.2_SSD 1 Key M
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PCIE_PCH + 24, // TBT 0
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PCIE_PCH + 8, // TBT 1
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NOT_USED,
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NOT_USED,
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NOT_USED
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}}
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)}
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr4SODimmCrb]
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gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
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{{
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PCIE_PEG + 1, // x16 PEG Slot
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NOT_USED,
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PCIE_PCH + 12, // PCIE x4 Slot 1
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 6, // Foxville
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 7, // M.2_WLAN
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PCIE_PCH + 1, // M.2_WWAN
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PCIE_PEG, // CPU_M.2 Key M
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PCIE_PCH + 20, // M.2_SSD 1 Key M
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PCIE_PCH + 24, // TBT
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NOT_USED,
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NOT_USED,
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NOT_USED,
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NOT_USED
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}}
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)}
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr5SODimmAep]
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gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
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{{
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PCIE_PEG + 1, // x16 PEG Slot
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NOT_USED,
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 6, // Foxville
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NOT_USED,
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NOT_USED,
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NOT_USED,
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PCIE_PCH + 24, // M.2_WLAN
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PCIE_PCH + 1, // M.2_WWAN
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PCIE_PCH + 20, // PCH SSD2
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PCIE_PCH + 12, // PCH SSD1
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PCIE_PCH + 8, // TBT 0
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NOT_USED,
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NOT_USED,
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NOT_USED,
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NOT_USED
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}}
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)}
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