220 lines
8.1 KiB
Plaintext
220 lines
8.1 KiB
Plaintext
/** @file
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;******************************************************************************
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;* Copyright (c) 2020 - 2021, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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/*
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== Readme ==
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For NVOP support, SBIOS has to adjust below code to meet platform:
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- Modify the method path of \_SB.PCI0.PGON and \_SB.PCI0.PGOF to Intel RC dGPU ON/OFF method
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- Modify enable the GPI event for illustrating the GPE event from HPD to notify 0x81
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to dGPU for HPD handling when dGPU is Off.
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*/
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//
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// Note: Following sample code is added into Gpe.asl (_L61 event) for CRB.
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// Please based on your project design to add this notification into
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// corresponding event.
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//
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// IBV should be to follow the below defines to support HPD notification.
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// Example:
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// HDMI or DP HotPlug evnet GPIO pin
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// 1. Connect to PCH
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// GPI event number: _L61
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// #define HPD_L_EVENT_NUMBER _L61
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// #define EVENT_DEVICE_PATH \_GPE
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//
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// 2. Connect to EC
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// GPI evennt enumber: Q21
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// #define HPD_L_EVENT_NUMBER Q21
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// #define EVENT_DEVICE_PATH \_SB.PCI0.SBRG.EC0
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//
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// DGPU device path: \_SB.PCI0.PEG0.PEGP
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// #define DGPU_DEVICE_PATH \_SB.PCI0.PEG0.PEGP
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//#ifdef HPD_L_EVENT_NUMBER
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// External (EVENT_DEVICE_PATH, DeviceObj)
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// Scope (EVENT_DEVICE_PATH)
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// {
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// Method (HPD_L_EVENT_NUMBER, 0, NotSerialized) // _Lxx: Level-Triggered GPE
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// {
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// Notify (DGPU_DEVICE_PATH, 0x81) // Information Change
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// }
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// }
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//#endif
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Scope (DGPU_SCOPE)
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{
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Name (VGAB, Buffer(0xFB)
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{
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0x00
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})
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Method (_PS0, 0)
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{
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If (LNotEqual (DGPS, Zero))
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{
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DGPU_BRIDGE_SCOPE.PXP._ON ()
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If (LNotEqual (GPRF, One))
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{
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Store (VGAB, VGAR)
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}
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Store (Zero, DGPS)
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}
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}
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Method (_PS3, 0)
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{
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If (LEqual (OMPR, 0x3))
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{
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If (LNotEqual (GPRF, One))
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{
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Store (VGAR, VGAB)
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}
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DGPU_BRIDGE_SCOPE.PXP._OFF ()
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Store (One, DGPS)
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Store (0x2, OMPR)
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}
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}
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Name (DGPS, Zero)
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Name (OMPR, 0x2) // Optimus MXM Power-Control Ready
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Name (GPRF, Zero)
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Name (DPST, One)
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Method (NVOP, 4, Serialized)
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{
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Store ("------- NV OPTIMUS DSM --------", Debug)
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// Only Interface Revision 0x0100 is supported
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If (LNotEqual (Arg1, 0x100))
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{
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Return (STATUS_ERROR_UNSPECIFIED)
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}
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// (Arg2) Sub-Function
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Switch (ToInteger (Arg2))
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{
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//
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// Function 0: NVOP_FUNC_SUPPORT - Bit list of supported functions.
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//
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case (NVOP_FUNC_SUPPORT)
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{
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Store (" NVOP fun0 NVOP_FUNC_SUPPORT", Debug)
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Return (Buffer(0x04)
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{
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// sub-func: 0,26,27 supported
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0x01, 0x00, 0x00, 0x0C
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})
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}
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//
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// Function 26: NVOP_FUNC_OPTIMUSCAPS - Optimus Capabilities.
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//
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case (NVOP_FUNC_OPTIMUSCAPS)
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{
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Store (" NVOP fun26 NVOP_FUNC_OPTIMUSCAPS", Debug)
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CreateField (Arg3, 0, 1, FLCH)
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CreateField (Arg3, 1, 1, DVSR) // Modify Optimus DSM 0x1A for GC6 TDR support.
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CreateField (Arg3, 2, 1, DVSC) // Modify Optimus DSM 0x1A for GC6 TDR support.
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CreateField (Arg3, 24, 2, OPCE)
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If (LAnd (ToInteger (FLCH), LNotEqual (ToInteger (OPCE), OMPR)))
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{
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Store (ToInteger (OPCE), OMPR) // Optimus Power Control Enable - From DD
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}
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// Definition of return buffer.
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// bit 0 - Optimus Enabled
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// 0 : Optimus Graphics Disabled
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// 1 : Optimus Graphics Enabled (default)
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// bit 4:3 - Current GPU Control Status
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// 0 : GPU is powered off
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// 3 : GPU power has stabilized (default)
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// bit 6 - Shared discrete GPU Hot-Plug Capabilities
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// 1 : There are discrete GPU Display Hot-Plug signals co-connected to the platform
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// bit 8 - PCIe Configuration Space Owner Actual
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// 0 : SBIOS
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// 1 : GPU Driver
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// bit 26:24 - Optimus Capabilities
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// 0 : No special platform capabilities
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// 1 : Platform has dynamic GPU power control
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// bit 27:28 - Optimus HD Audio Codec Capabilities
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// 0 : No audio codec-related capabilities
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// 1 : Platform does not use HD audio
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// 2 : Platform supports Optimus dynamic codec control
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Store (Buffer(4) {0, 0, 0, 0}, Local0)
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CreateField (Local0, 0, 1, OPEN)
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CreateField (Local0, 3, 2, CGCS)
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CreateField (Local0, 6, 1, SHPC) // Shared discrete GPU Hot-Plug Capabilities
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CreateField (Local0, 8, 1, SNSR) // Modify Optimus DSM 0x1A for GC6 TDR support.
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CreateField (Local0, 24, 3, DGPC) // Optimus Power Capabilities
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CreateField (Local0, 27, 2, OHAC) // Optimus HD Audio Codec Capabilities
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Store (One, OPEN) // Optimus Enabled
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Store (One, SHPC) // Set '1' indicates there are discrete GPU Display Hot-Plug signals co-connected to the platform
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Store (One, DGPC) // Optimus Power Capabilities
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// 0: No special platform capabilities
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// 1: Dynamic GPU Power Control
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Store (0x3, OHAC) // Optimus HD Audio Codec Capabilities
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// 0: No audio codec-related capabilities
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// 1: Platform does not use HD audio (SBIOS will always disable audio codecs)
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// 2: Optimus dynamic codec control
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// 3: Dynamic power state reporting
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If (ToInteger (DVSC))
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{
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If (ToInteger (DVSR))
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{
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Store (One, GPRF)
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}
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Else
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{
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Store (Zero, GPRF)
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}
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}
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Store (GPRF, SNSR)
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If (LEqual (DGPS, Zero))
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{
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Store (0x3, CGCS) // Current GPU Control status: On
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}
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ELSE
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{
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Store (0x0, CGCS) // Current GPU Control status: Off
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}
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Return (Local0)
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}
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//
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// Function 27: NVOP_FUNC_OPTIMUSFLAGS - Optimus State flags.
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//
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case (NVOP_FUNC_OPTIMUSFLAGS)
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{
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Store (" NVOP fun27 NVOP_FUNC_OPTIMUSFLAGS", Debug)
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CreateField (Arg3, 0x00, 1, OACC) // Optimus Audio Codec Control
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CreateField (Arg3, 0x01, 1, UOAC) // Update Optimus Audio Codec Control
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CreateField (Arg3, 0x02, 8, OPDA) // Count of the number of applications running on the dGPU
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CreateField (Arg3, 0x0A, 1, OPDE) // Indicate bit 9:2 valid or not
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Store (Zero, Local1)
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Store (DGPU_SCOPE.HDAE, Local1) // Returns the currnet status of the audio device
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Return (Local1)
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}
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default
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{
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//
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// FunctionCode or SubFunctionCode not supported
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//
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Return (STATUS_ERROR_UNSUPPORTED)
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}
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}
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}
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} |