109 lines
5.5 KiB
C
109 lines
5.5 KiB
C
/** @file
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;******************************************************************************
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;* Copyright (c) 2014, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#ifndef I2C_REGS_H_
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#define I2C_REGS_H_
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#define MAX_I2C_BUS_NUM 6
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//
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// MMI/O Register Definitions
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//
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#define R_IC_CON 0x00
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#define B_IC_RESTART_EN BIT5
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#define B_IC_SLAVE_DISABLE BIT6
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#define V_SPEED_STANDARD 0x02
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#define V_SPEED_FAST 0x04
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#define V_SPEED_HIGH 0x06
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#define B_MASTER_MODE BIT0
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#define R_IC_TAR 0x04 // I2C Target Address
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#define R_IC_SAR 0x08 // I2C Slave Address
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#define R_IC_HS_MADDR 0x0C // I2C HS MasterMode Code Address
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#define R_IC_DATA_CMD 0x10 // I2C Rx/Tx Data Buffer and Command
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#define B_READ_CMD BIT8 // 1 = read, 0 = write
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#define B_WRITE_CMD 0x00 // 1 = read, 0 = write
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#define B_STOP_CMD BIT9
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#define B_RESTART_CMD BIT10
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#define V_WRITE_CMD_MASK 0xFF
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#define R_IC_SS_SCL_HCNT 0x14 // Standard Speed I2C Clock SCL High Count
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#define R_IC_SS_SCL_LCNT 0x18 // Standard Speed I2C Clock SCL Low Count
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#define R_IC_FS_SCL_HCNT 0x1C // Full Speed I2C Clock SCL High Count
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#define R_IC_FS_SCL_LCNT 0x20 // Full Speed I2C Clock SCL Low Count
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#define R_IC_HS_SCL_HCNT 0x24 // High Speed I2C Clock SCL High Count
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#define R_IC_HS_SCL_LCNT 0x28 // High Speed I2C Clock SCL Low Count
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#define R_IC_INTR_STAT 0x2C // I2C Inetrrupt Status
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#define R_IC_INTR_MASK 0x30 // I2C Interrupt Mask
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#define B_I2C_INTR_GEN_CALL BIT11 // General call received
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#define B_I2C_INTR_START_DET BIT10
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#define B_I2C_INTR_STOP_DET BIT9
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#define B_I2C_INTR_ACTIVITY BIT8
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#define B_I2C_INTR_TX_ABRT BIT6 // Set on NACK
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#define B_I2C_INTR_TX_EMPTY BIT4
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#define B_I2C_INTR_TX_OVER BIT3
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#define B_I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
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#define B_I2C_INTR_RX_OVER BIT1
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#define B_I2C_INTR_RX_UNDER BIT0
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#define R_I2C_RAW_INTR_STAT 0x34 // I2C Raw Interrupt Status
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#define R_I2C_RX_TL 0x38 // I2C Receive FIFO Threshold
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#define R_I2C_TX_TL 0x3C // I2C Transmit FIFO Threshold
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// #define R_IC_CLR_INTR 0x40 // Clear Combined and Individual Interrupts
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// #define R_IC_CLR_RX_UNDER 0x44 // Clear RX_UNDER Interrupt
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// #define R_IC_CLR_RX_OVER 0x48 // Clear RX_OVERinterrupt
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// #define R_IC_CLR_TX_OVER 0x4C // Clear TX_OVER interrupt
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// #define R_IC_CLR_RD_REQ 0x50 // Clear RD_REQ interrupt
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#define R_I2C_CLR_TX_ABRT 0x54 // Clear TX_ABRT interrupt
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// #define R_IC_CLR_RX_DONE 0x58 // Clear RX_DONE interrupt
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// #define R_IC_CLR_ACTIVITY 0x5C // Clear ACTIVITY interrupt
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// #define R_IC_CLR_STOP_DET 0x60 // Clear STOP_DET interrupt
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// #define R_IC_CLR_START_DET 0x64 // Clear START_DET interrupt
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// #define R_IC_CLR_GEN_CALL 0x68 // Clear GEN_CALL interrupt
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#define R_I2C_ENABLE 0x6C // I2C Enable
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#define B_IC_ENABLE_EN BIT0
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#define B_IC_ENABLE_DIS 0
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#define R_IC_STATUS 0x70 // I2C Status
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#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
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#define STAT_RFF BIT4 // RX FIFO is completely full
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#define STAT_RFNE BIT3 // RX FIFO is not empty
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#define STAT_TFE BIT2 // TX FIFO is completely empty
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#define STAT_TFNF BIT1 // TX FIFO is not full
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#define R_IC_TXFLR 0x74 // Transmit FIFO Level Register
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// #define R_IC_RXFLR 0x78 // Receive FIFO Level Register
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// #define R_IC_TX_ABRT_SOURCE 0x80 // I2C Transmit Abort Status Register
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#define R_I2C_SDA_HOLD 0x7C
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#define R_IC_SLV_DATA_NACK_ONLY 0x84 // Generate SLV_DATA_NACK Register
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#define R_IC_DMA_CR 0x88 // DMA Control Register
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#define R_IC_DMA_TDLR 0x8C // DMA Transmit Data Level
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#define R_IC_DMA_RDLR 0x90 // DMA Receive Data Level
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#define R_I2C_ENABLE_STATUS 0x9C // I2C Enable Status Register
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// #define R_IC_COMP_PARAM 0xF4 // Component Parameter Register
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// #define R_IC_COMP_VERSION 0xF8 // Component Version ID
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// #define R_IC_COMP_TYPE 0xFC // Component Type
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#endif // I2C_REGS_H
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