344 lines
13 KiB
C
344 lines
13 KiB
C
/** @file
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Chipset Setup Configuration Definitions
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;******************************************************************************
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;* Copyright (c) 2014 - 2018, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#ifndef _CHIPSET_SETUP_CONFIG_H_
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#define _CHIPSET_SETUP_CONFIG_H_
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#ifndef VFRCOMPILE
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#include <Uefi/UefiInternalFormRepresentation.h>
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#endif
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#include <KernelSetupConfig.h>
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#include <IccSetupData.h>
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// #include <PlatformBoardId.h> // gino: temp remove
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#include <Setup.h>
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#include <SetupId.h>
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#include <SetupVariable.h>
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#include <OemSetup.h>
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#define DVMT_PREALLOCATE_LABEL 0x1060
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#define KEY_TXT 0x20B4
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#define IDE_UPDATE_LABEL 0x1005
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#define AZALIA_LABEL 0x1006
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#define CORE_RATIO_LIMIT_LABEL 0x1051
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#define SYSTEM_HEALTH_LABEL 0x1013
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#define DUAL_VGA_SUPPORT_START_LABEL 0x1cfe
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#define DUAL_VGA_SUPPORT_END_LABEL 0x1cff
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#define PLUG_IN_DISPLAY_SELECTION_START_LABEL 0x1d00
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#define PLUG_IN_DISPLAY_SELECTION_END_LABEL 0x1d01
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#define IGD_DISPLAY_SELECTION_START_LABEL 0x1d02
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#define IGD_DISPLAY_SELECTION_END_LABEL 0x1d03
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#define APCI_DEBUG_ADDRESS_LABEL 0x1052
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// #define PTT_INFO_LABEL 0x1055
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// #define PTT_ENABLE_LABEL 0x660
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// #define PTT_REVOKE_TRUST_LABEL 0x1670
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#define ME_UNCONFIG_ON_RTC_LABEL 0x671
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#define KEY_SERIAL_PORTA 0x2030
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#define KEY_SERIAL_PORTA_BASE_IO 0x2031
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#define KEY_SERIAL_PORTA_INTERRUPT 0x2032
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#define KEY_SERIAL_PORTB 0x2033
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#define KEY_SERIAL_PORTB_BASE_IO 0x2034
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#define KEY_SERIAL_PORTB_INTERRUPT 0x2035
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#define KEY_PCI_SLOT3_IRQ_SET 0x2040
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#define KEY_PCI_SLOT4_IRQ_SET 0x2041
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#define KEY_PEG_FORCE_X1 0x2050
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#define KEY_PCIE_COMPLIANCE_MODE 0x2051
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#define KEY_CHIPSET_EXTENDED_CONFIG 0x2060
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#define KEY_CHIPSET_SDRAM_TIME_CTRL 0x2061
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#define KEY_SETUP_REFRESH 0x2062
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#define KEY_PCI_IRQ_SET 0x2063
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#define KEY_AHCI_OPROM_CONFIG 0x2065
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#define KEY_SATA_CNFIGURE_MODE 0x2090
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#define KEY_DUAL_VGA_SUPPORT 0x2066
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#define KEY_PLUG_IN_DISPLAY_SELECTION1 0x21d0
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#define KEY_PLUG_IN_DISPLAY_SELECTION2 0x21d1
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#define KEY_IGD_PRIMARY_DISPLAY_SELECTION 0x21e0
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#define KEY_IGD_SECONDARY_DISPLAY_SELECTION 0x21e1
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#define ME_IMAGE_CONSUMER_SKU_FW 0x03
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#define ME_IMAGE_CORPORATE_SKU_FW 0x04
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#define KEY_DVMT_PREALLOCATE 0xA00
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#define KEY_APERTURE_SIZE 0xA04
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#define KEY_WAKE_ON_PME 0x402
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#define KEY_DPTF 0x3610
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#define KEY_PROCESSOR_THERMAL 0x3620
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#define KEY_XHCI_PREBOOT_SUPPORT 0x600
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#define KEY_IFR_UPDATE 0x610
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#define KEY_DDR3LV_OPTION 0x620
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#define KEY_MAX_TOLUD_OPTION 0x630
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#define IDE_MODE 0
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#define AHCI_MODE (SATA_MODE_AHCI + 1)
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#define RAID_MODE (SATA_MODE_RAID + 1)
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//#define LOOPBACK_TEST_MODE 3
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#define KEY_PCI_EXPRESS_CONFIGURATION_CHANGE 0x61
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#define KEY_CPU_CONTROL 0x652
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#define KEY_ME_UNCONFIG_ON_RTC 0x670
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#define LABEL_CPU_RATIO 0x683
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#define SERIAL_ATA_PORT0_FORM_ID 0x230
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#define SERIAL_ATA_PORT1_FORM_ID 0x231
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#define SERIAL_ATA_PORT2_FORM_ID 0x232
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#define SERIAL_ATA_PORT3_FORM_ID 0x233
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#define SERIAL_ATA_PORT4_FORM_ID 0x234
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#define SERIAL_ATA_PORT5_FORM_ID 0x235
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#define SERIAL_ATA_PORT6_FORM_ID 0x236
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#define SERIAL_ATA_PORT7_FORM_ID 0x237
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#define KEY_OTHER_VFR_GOTO_BASE 0x3000
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#define SERIAL_IO_FORM_ID 0x3700
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#define SERIAL_IO_I2C0_FORM_ID 0x3701
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#define SERIAL_IO_I2C1_FORM_ID 0x3702
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#define SERIAL_IO_I2C2_FORM_ID 0x3703
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#define SERIAL_IO_I2C3_FORM_ID 0x3704
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#define SERIAL_IO_I2C4_FORM_ID 0x3705
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#define SERIAL_IO_I2C5_FORM_ID 0x3706
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#define SERIAL_IO_SPI0_FORM_ID 0x3707
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#define SERIAL_IO_SPI1_FORM_ID 0x3708
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#define SERIAL_IO_SPI2_FORM_ID 0x3709
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#define SERIAL_IO_UART0_FORM_ID 0x370A
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#define SERIAL_IO_UART1_FORM_ID 0x370B
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#define SERIAL_IO_UART2_FORM_ID 0x370C
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#define SERIAL_IO_GPIO_FORM_ID 0x370D
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#define SERIAL_IO_TIMING_FORM_ID 0x370E
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#define SCS_FORM_ID 0x3720
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#define ISH_FORM_ID 0x3730
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#define HD_AUDIO_FORM_ID 0x3710
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#define HD_AUDIO_ADVANCED_CONFIG_FORM_ID 0x3711
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#define HD_AUDIO_DSP_FEATURE_CONFIGFORM_ID 0x3712
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#define SKYCAM_FORM_ID 0x3750
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#define SKYCAM_CONTROL_lOGIC_0_FORM_ID 0x3751
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#define SKYCAM_CONTROL_lOGIC_1_FORM_ID 0x3752
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#define SKYCAM_CONTROL_lOGIC_2_FORM_ID 0x3753
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#define SKYCAM_CONTROL_lOGIC_3_FORM_ID 0x3754
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#define SKYCAM_LINK_0_FORM_ID 0x3755
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#define SKYCAM_LINK_1_FORM_ID 0x3756
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#define SKYCAM_LINK_2_FORM_ID 0x3757
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#define SKYCAM_LINK_3_FORM_ID 0x3758
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#define MAX_PCI_EXPRESS_ROOT_PORTS 6
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//
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// Express Card Support
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//
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#define EXPRESS_CARD_ROOT_PORT_BUS 0x0
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#define EXPRESS_CARD_ROOT_PORT_DEV PCI_DEVICE_NUMBER_ICH_PCIEXP
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#define EXPRESS_CARD_ROOT_PORT_FUN PCI_FUNCTION_NUMBER_ICH_PCIEXP2
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//
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// Local Flat Panel Backlight Control Mode , refer to VBIOS Int15 sub:5F49h
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//
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#define BKLT_SEL_PWM_INVERTED 0
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#define BKLT_SEL_PWM_NORMAL 2
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#define BKLT_SEL_GMBUS_INVERTED 1
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#define BKLT_SEL_GMBUS_NORMAL 3
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#define B_C1_AUTO_DEMOTION BIT0
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#define B_C3_AUTO_DEMOTION BIT1
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#define B_C1_UNDEMOTION BIT0
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#define B_C3_UNDEMOTION BIT1
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#define B_TS_ON_DIMM_SLOT0 BIT0
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#define B_TS_ON_DIMM_SLOT1 BIT1
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#define DUAL_VGA_CONTROLLER_ENABLE 1
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#define DUAL_VGA_CONTROLLER_DISABLE 0
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//
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// DisplayMode
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//
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#define DISPLAY_MODE_IGPU 0x0
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#define DISPLAY_MODE_DGPU 0x1
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#define DISPLAY_MODE_PCI 0x2
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#define DISPLAY_MODE_AUTO 0x3
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#define DISPLAY_MODE_HYBRID 0x4
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#define DUAL_VGA_CONTROLLER_ENABLE 1
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#define DUAL_VGA_CONTROLLER_DISABLE 0
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#define SCU_IGD_BOOT_TYPE_DISABLE 0x00
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#define SCU_IGD_BOOT_TYPE_VBIOS_DEFAULT 0x00
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#define SCU_IGD_BOOT_TYPE_CRT 0x01
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#define SCU_IGD_BOOT_TYPE_LFP 0x08
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#define SCU_IGD_BOOT_TYPE_EFP 0x04
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#define SCU_IGD_BOOT_TYPE_EFP3 0x20
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#define SCU_IGD_BOOT_TYPE_EFP2 0x40
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#define SCU_IGD_BOOT_TYPE_LFP2 0x80
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#define IGD_ENABLE 1
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#define IGD_DISABLE 0
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#define IGD_AUTO 2
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#define ALWAYS_ENABLE_PEG 1
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#define DONT_ALWAYS_ENABLE_PEG 1
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#define SG_ENABLE 1
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#define SG_DISABLE 0
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#define MUXED_FIXED 1
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#define MUXLESS_FIXED 5
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#define MUXLESS_DYNAMIC 6
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#define MUXLESS_FIXED_DYNAMIC 7
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#define SCU_IGD_BOOT_TYPE_DISABLE 0x00
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#define SCU_IGD_BOOT_TYPE_VBIOS_DEFAULT 0x00
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#define SCU_IGD_BOOT_TYPE_CRT 0x01
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#define SCU_IGD_BOOT_TYPE_LFP 0x08
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#define SCU_IGD_BOOT_TYPE_EFP 0x04
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#define SCU_IGD_BOOT_TYPE_EFP3 0x20
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#define SCU_IGD_BOOT_TYPE_EFP2 0x40
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#define SCU_IGD_BOOT_TYPE_LFP2 0x80
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//
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// The order is for SCU
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//
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#define SCU_IGD_INDEX_DISABLE 0x00
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#define SCU_IGD_INDEX_VBIOS_DEFAULT 0x00
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#define SCU_IGD_INDEX_CRT 0x01
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#define SCU_IGD_INDEX_LFP 0x02
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#define SCU_IGD_INDEX_EFP 0x03
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#define SCU_IGD_INDEX_EFP2 0x04
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#define SCU_IGD_INDEX_EFP3 0x05
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#define SCU_IGD_INDEX_LFP2 0x06
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#define FAST_RECLAIM_COUNT 35
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#define ADVANCE_VARSTORE_ID 0x1233
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#define CONFIGURATION_VARSTORE_ID 0x1234
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#define MAX_HII_HANDLES 0x10
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#define INVALID_HII_HANDLE 0
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#define TPM2_DISABLE 0
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#define TPM2_ENABLE 1
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#define PTT_DISABLE 0
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#define PTT_ENABLE 1
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#define LPC_PCH_TYPE_LP 1
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#define LPC_PCH_TYPE_H 0
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#define XMP_MEM_AUTO 0
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#define SGX_FACTORY_PRESET_EPOCH 0
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#define SGX_RANDOM_GENERATED_EPOCH 1
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#define SGX_USER_MANUAL_EPOCH 2
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//
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// SkylakeSiPkg\SystemAgent\Include\Ppi\GraphicsConfig.h
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// GT Aperture Size
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//
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#define GTAPERTURESIZE128MB 0
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#define GTAPERTURESIZE256MB 1
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#define GTAPERTURESIZE512MB 3
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#define GTAPERTURESIZE1024MB 7
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#define GTAPERTURESIZE2048MB 15
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#define GTAPERTURESIZE4096MB 31
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#define OFFSET_0 0x0
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#define OFFSET_1 0x1
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#define OFFSET_2 0x2
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#define OFFSET_3 0x3
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#define OFFSET_4 0x4
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#define OFFSET_5 0x5
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#define OFFSET_6 0x6
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#define OFFSET_7 0x7
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#define OFFSET_8 0x8
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#define OFFSET_9 0x9
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#define OFFSET_10 0xa
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#define OFFSET_11 0xb
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#define OFFSET_12 0xc
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#define OFFSET_13 0xd
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#define OFFSET_14 0xe
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#define OFFSET_15 0xf
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#define OFFSET_16 0x10
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#define OFFSET_17 0x11
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#define OFFSET_18 0x12
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#define OFFSET_19 0x13
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#define OFFSET_20 0x14
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#define OFFSET_21 0x15
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#define OFFSET_22 0x16
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#define OFFSET_23 0x17
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#define OFFSET_24 0x18
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#define OFFSET_25 0x19
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#define OFFSET_26 0x1a
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#define OFFSET_27 0x1b
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#define OFFSET_28 0x1c
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#define OFFSET_29 0x1d
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#define OFFSET_30 0x1e
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#define OFFSET_31 0x1f
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#define OFFSET_32 0x20
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#define OFFSET_33 0x21
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#define OFFSET_34 0x22
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#define OFFSET_35 0x23
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#define OFFSET_36 0x24
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#define OFFSET_37 0x25
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#define OFFSET_38 0x26
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#define OFFSET_39 0x27
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#define MAIN_FORM_SET_CLASS 0x1
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#define ADVANCED_FORM_SET_CLASS 0x2
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#define ICC_CLOCK_SETTING_TYPE_CURRENT 0
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#define ICC_CLOCK_SETTING_TYPE_BOOT 1
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#define ICC_CLOCK_SETTING_TYPE_PRE_BOOT 2
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#define ICC_CLOCK_SETTING_TYPE_OEM 3
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extern EFI_GUID gChipsetSetupDafultGuid;
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extern SETUP_DATA mSetupData;
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extern SA_SETUP mSaSetup;
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extern ME_SETUP mMeSetup;
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extern CPU_SETUP mCpuSetup;
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extern PCH_SETUP mPchSetup;
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extern SETUP_VOLATILE_DATA mSetupVolatileData;
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#pragma pack(1)
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typedef struct {
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UINT8 IdeDevice0;
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UINT8 IdeDevice1;
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UINT8 IdeDevice2;
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UINT8 IdeDevice3;
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UINT8 IdeDevice4;
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UINT8 IdeDevice5;
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UINT8 IdeDevice6;
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UINT8 IdeDevice7;
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} ADVANCE_CONFIGURATION;
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#pragma pack()
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#pragma pack(1)
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//
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// Setup Utility Structure
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Important!!! The following setup utility structure should be syncronize with OperationRegion MBOX in mailbox.asi.
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// If you do NOT follow it, you may face on unexpected issue. The total size are 1200 bytes.
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// (Kernel 230 bytes + OEM 70 bytes + ODM 100 bytes + Chipset 800 bytes)
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//-----------------------------------------------------------------------------------------------------------------
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typedef struct {
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//
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// Kernel system configuration (offset 0~229, total 230 bytes)
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//
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#define _IMPORT_KERNEL_SETUP_
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#include <KernelSetupData.h>
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#undef _IMPORT_KERNEL_SETUP_
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// OEM_Start
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// Offset 230~299, total 70 bytes; // This area must sync to SetupConfig.h
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UINT8 OEMRSV[70]; // Dummy area. Reserve for OEM team, really structure will fill in SetupConfig.h
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// OEM_End
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// ODM_Start
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// Offset 300~399, total 100 bytes; // This are must sync to SetupConfig.h
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UINT8 ODMRSV[100]; // Dummy area. Reserve for ODM, really structure will fill in SetupConfig.h
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// ODM_End
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//
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// Chipset system configuration (offset 400~1199, total 800 bytes)
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//
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#define _IMPORT_CHIPSET_SPECIFIC_SETUP_
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#include <ChipsetSpecificSetupData.h>
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#undef _IMPORT_CHIPSET_SPECIFIC_SETUP_
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} CHIPSET_CONFIGURATION;
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#pragma pack()
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#endif
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