280 lines
10 KiB
C
280 lines
10 KiB
C
/** @file
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This header file provides platform specific definitions used by other modules
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for platform specific initialization.
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THIS FILE SHOULD ONLY CONTAIN #defines BECAUSE IT IS CONSUMED BY NON-C MODULES
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(ASL and VFR)
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This file should not contain addition or other operations that an ASL compiler or
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VFR compiler does not understand.
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@copyright
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Copyright (c) 1999 - 2014 Intel Corporation. All rights reserved
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This software and associated documentation (if any) is furnished
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under a license and may only be used or copied in accordance
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with the terms of the license. Except as permitted by such
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license, no part of this software or documentation may be
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reproduced, stored in a retrieval system, or transmitted in any
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form or by any means without the express written consent of
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Intel Corporation.
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This file contains an 'Intel Peripheral Driver' and is
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licensed for Intel CPUs and chipsets under the terms of your
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license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the
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license agreement.
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**/
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#ifndef _PLATFORM_DEFINITIONS_H_
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#define _PLATFORM_DEFINITIONS_H_
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//
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// Platform Base Address definitions
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//
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#define PCIEX_BASE_ADDRESS (UINTN) PcdGet64 (PcdPciExpressBaseAddress) // Pci Express Configuration Space Base Address
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#define PLATFORM_PCIEXPRESS_LENGTH (UINT32) PcdGet32 (PcdPciExpressRegionLength)
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#define PCIEX_LENGTH PLATFORM_PCIEXPRESS_LENGTH
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#define HPET_ADDRESS_0 0xFED00000
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#define HPET_ADDRESS_1 0xFED01000
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#define HPET_ADDRESS_2 0xFED02000
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#define HPET_ADDRESS_3 0xFED03000
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#define HPET_MMIO_SIZE 0x4000 // Report all range for simple
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#define THERMAL_BASE_ADDRESS 0xFED08000
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#ifndef MCH_BASE_ADDRESS
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#define MCH_BASE_ADDRESS 0xFED10000 // MCH Register Base Address
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#endif
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// From Client SNB EDS 0.7v3, 32KB window
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#define MCH_MMIO_SIZE 0x8000 // MCH Register MMIO Size
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#define HECIF0_BASE_ADDRESS 0xFED1A000 // HECI Function 0 Register Base Address
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// --cr HECI MMIO size window to be fixed
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#define HECIF1_BASE_ADDRESS 0xFED1B000 // HECI Function 1 Register Base Address
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#define DMI_BASE_ADDRESS 0xFED18000 // DMI Register Base Address
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// From Client SNB EDS 0.7v3, 4KB window
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#define DMI_MMIO_SIZE 0x1000 // DMI Register MMIO Size
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#define EP_BASE_ADDRESS 0xFED19000 // EP Register Base Address
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// From Client SNB EDS 0.7v3, 4KB window
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#define EP_MMIO_SIZE 0x1000 // EP Register MMIO Size
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#define GDXC_BASE_ADDRESS 0xFED84000 // GDXC Register Base Address
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#define GDXC_MMIO_SIZE 0x1000 // GDXC Register MMIO Size = 4KB
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#define EDRAM_BASE_ADDRESS 0xFED80000 // EDRAM Register Base Address
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#define EDRAM_MMIO_SIZE 0x4000 // EDRAM Register MMIO Size = 16KB
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#define EFI_APIC_LOCAL_ADDRESS 0xFEE00000
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#define APIC_LOCAL_MMIO_SIZE 0x1000
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#define EFI_APIC_IO_ADDRESS_PCH 0xFEC00000
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#define APIC_IO_MMIO_SIZE 0x1000
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#define GTTMM_ADDRESS 0x3E000000 // GTTMMADR ADDRESS
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#define GTTMM_SIZE 0x400000 // GTT SIZE
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#define PCH_ACPI_BASE_ADDRESS 0x1800 // ACPI Power Management I/O Register Base Address
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#define PCH_ACPI_P_BLK_ADDRESS 0x1810
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#define PCH_ACPI_TIMER_ADDR 0x1808
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#define PCH_ACPI_TIMER_MAX_VALUE 0x1000000 // The timer is 24 bit overflow
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#define PCH_TCO_BASE_ADDRESS 0x400 // This value must the same as PcdTcoBaseAddress
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#define PCH_TCO1_STS_REGISTER 0x1864
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#define PM_BASE_ADDRESS PCH_ACPI_BASE_ADDRESS
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#define SIO_BASE_ADDRESS 0x0680
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#define SIO_BASE_ADDRESS2 0x1640
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#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690
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#define PCH_SMBUS_BASE_ADDRESS 0xEFA0
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#define PCH_GPIO_BASE_ADDRESS 0x0800
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#define GPIO_BASE_ADDRESS PCH_GPIO_BASE_ADDRESS
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//
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// RTC software information
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//
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#define PCAT_RTC_ADDRESS_REGISTER 0x70
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#define PCAT_RTC_DATA_REGISTER 0x71
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#define RTC_ADDRESS_REGISTER_D 13
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//
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// APIC definitions
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//
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#define EFI_APIC_IO_ID_PCH 0x02
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//
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// ACPI software SMI numbers
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//
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#define EFI_ACPI_ENABLE_SW_SMI 0xA0
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#define EFI_ACPI_DISABLE_SW_SMI 0xA1
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//#define EFI_PEP_BCCD_SW_SMI 0xCD
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#define FW_WRITE 0x42
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#define FW_UPDATE 0x43
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#define BIS_DATA_READ 0x45
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#define BIS_DATA_WRITE 0x46
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#define S3_RESTORE_MSR_SW_SMI 0x48
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#define FLASH_WRITE_PROTECT_POST_COMPLETED_SW_SMI 0x49
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#define EFI_ACPI_LVMM_SW_SMI 0x4A
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#define PCIE_DOCK_BRIDGE_RESOURCE_PATCH_SMI 0x4D
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#define INTEL_3945ABG_AUTO_DETECT_WORKAROUND_SMI 0x50
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#define SET_DISPLAY_DEVICE_SMI 00
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#define GET_CURRENT_DISPLAY_DEVICE_SMI 01
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#define GET_DISPLAY_DEVICE_DETECT_SMI 02
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#define GET_NEXT_DISPLAY_DEVICE_SMI 05
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#define DISPLAY_SWITCH_TOGGLE_ACPI_SMI 10
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#define DISPLAY_SWITCH_TOGGLE_LEGACY_SMI 11
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#define DISPLAY_SWITCH_LID_OPEN_ACPI_SMI 12
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#define DISPLAY_SWITCH_LID_OPEN_LEGACY_SMI 13
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#define DISPLAY_SWITCH_LID_CLOSE_ACPI_SMI 14
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#define DISPLAY_SWITCH_LID_CLOSE_LEGACY_SMI 15
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#define POPUP_ICON_TOGGLE_SMI 16
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#define SET_HOR_VERT_COMPENSATION_SMI 17
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#define SET_BACKLIGHT_CONTROL_SMI 18
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#define SET_ALI_LEVEL_SMI 19
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#define PCI_EXPRESS_HOT_PLUG_ADD_SMI 40
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#define PCI_EXPRESS_HOT_PLUG_REMOVE_SMI 41
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#define LID_STATE_SWITCH_SMI 42
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#define POWER_STATE_SWITCH_SMI 43
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#define HTT_LOGO_ENABLE_SMI 50
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#define HTT_THROTTLE_DISABLE_SMI 51
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#define HTT_THROTTLE_ENABLE_SMI 52
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#define SAVE_OSB_OS_TYPE_SMI 53
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#define ENABLE_C_STATE_IO_REDIRECTION_SMI 70
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#define DISABLE_C_STATE_IO_REDIRECTION_SMI 71
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#define ENABLE_SMI_C_STATE_COORDINATION_SMI 72
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#define DISABLE_SMI_C_STATE_COORDINATION_SMI 73
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#define ENABLE_P_STATE_HARDWARE_COORDINATION_SMI 74
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#define DISABLE_P_STATE_HARDWARE_COORDINATION_SMI 75
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#define SW_SMI_OVERCLOCKING_INTERFACE 0x72
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#define SW_SMI_POST_COMPLETE 0xbb
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//#define SW_SMI_FROM_SMMBASE 0x55
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//
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// Define some fixed platform device location information
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//
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#define DESKTOP_LPC_SIO_CONFIG_DEFAULT_PORT 0x2E
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#define DESKTOP_LPC_SIO_INDEX_DEFAULT_PORT 0x2E
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#define DESKTOP_LPC_SIO_DATA_DEFAULT_PORT 0x2F
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#define LPC_SIO_CONFIG_PORT 0x4E
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#define LPC_SIO_INDEX_PORT 0x4E
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#define LPC_SIO_DATA_PORT 0x4F
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#define LPC_SIO_CONFIG_DEFAULT_PORT 0x164E
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#define LPC_SIO_INDEX_DEFAULT_PORT 0x164E
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#define LPC_SIO_DATA_DEFAULT_PORT 0x164F
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#define LPC_SERIAL_PORT1_BASE 0x3F8
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#define LPC_SERIAL_PORT2_BASE 0x2F8
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//
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// GPIO[22] is used to detect recovery mode.
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//
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#define RECOVERY_DETECT_JUMPER BIT22
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//
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// Define the SMC EXTSMI# GPIO offset
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//
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#define SMC_EXTSMI_BIT_POSITION 1
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//
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// GPI Route Value( LPC + B8h) for SCI/EXTSMI/RUNTIME_SCI Gpio0~15.
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// SMI is two-bit-Pair(bit1:bit0) = 01
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// SCI is two-bit-Pair(bit1:bit0) = 10
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//
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#define PCH_GPI_ROUTE_SMI(Gpio) ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2))))
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#define PCH_GPI_ROUTE_SCI(Gpio) ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2))))
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//#define PCH_GPI_ROUTE (PCH_GPI_ROUTE_SMI(1) | PCH_GPI_ROUTE_SCI(7) | PCH_GPI_ROUTE_SCI(8))
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#define PCH_GPI_ROUTE (PCH_GPI_ROUTE_SCI(5)| PCH_GPI_ROUTE_SCI(7) | PCH_GPI_ROUTE_SCI(8))
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//
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// PCH Chipset platform specific interrupt route
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//
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#define PCH_D31IP 0x03243200
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#define PCH_D29IP 0x00014321
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#define PCH_D28IP 0x43214321
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#define PCH_D27IP 0x00000001
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#define PCH_D26IP 0x40000321
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#define PCH_D25IP 0x00000001
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#define PCH_D31IR 0x0230
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#define PCH_D29IR 0x2037
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#define PCH_D28IR 0x3210
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#define PCH_D27IR 0x3216
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#define PCH_D26IR 0x3250
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#define PCH_D25IR 0x7654
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#define PCH_D23IR 0x0006
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#define PCH_D21IR 0x5544
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#define PCH_D19IR 0x0007
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//
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// SmBus address to read DIMM SPD
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//
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#define PCH_SMBUS_BUS_DEV_FUNC 0x1F0400
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#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 4
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#define SMBUS_ADDR_CH_A_1 0xA0
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#define SMBUS_ADDR_CH_A_2 0xA2
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#define SMBUS_ADDR_CH_B_1 0xA4
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#define SMBUS_ADDR_CH_B_2 0xA6
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#include "PlatformClock.h"
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//
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// SMI I/O Trap Type
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//
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#define TRAP_TYPE_PPM 0x01
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#define TRAP_TYPE_DTS 0x02
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#define TRAP_TYPE_IGD 0x03
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//
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// This could change for different flash parts
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//
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#define EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH 0x48
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//
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// Define the offset in flash region of start of bios image
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// This definition needs to be updated based on the flash
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// map used and is only used for Non-descriptor mode. In descriptor
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// mode the base address of the BIOS is read from the flash
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// region 1 register.
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//
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#define BIOS_START_OFFSET 0x100000
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//
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// Define the offset between the EC critical thermal trip point
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// and the critical temperature reported to the OS via ACPI
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//
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#define EC_CRITICAL_THERMAL_OFFSET 0x0A
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//
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//
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//
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#define Smsc1007_PME_BASE_ADDRESS 0x680
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#define Thermal_Base_Address 0xfed08000
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#define SMBUS_BASE_ADDRESS 0xEFA0
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#define PLATFORM_DEBUG_PRINT_ERROR_LEVEL_VALUE 0x80000046 // DEBUG_ERROR|DEBUG_INFO|DEBUG_LOAD|DEBUG_WARN
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#define PLATFORM_SERIAL_BAUD_RATE_VALUE 115200
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#define CMOS_FAST_BOOT_REG_DEFAULT_VALUE 0x01
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//
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// Define TSEG size for platform
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//
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#define PLATFORM_TSEG_SIZE 0x1000000
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#endif
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