278 lines
7.8 KiB
C
278 lines
7.8 KiB
C
/** @file
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;******************************************************************************
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;* Copyright (c) 2019, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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/** @file
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Pei Serial Io Init Private Lib implementation.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2019 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef __PEI_SERIAL_IO_INIT_DDT_PRIVATE_LIB_H__
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#define __PEI_SERIAL_IO_INIT_DDT_PRIVATE_LIB_H__
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#include <Library/PsfLib.h>
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#include <Library/SerialIoPrivateLib.h>
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/**
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Enables SerialIo Power Gating
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@param[in] PciCfgBase Pci Config Offset
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**/
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VOID
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SerialIoEnablePowerGating (
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IN UINT64 PciCfgBase
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);
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/**
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Configures SerialIo to work on fixed address assignment only through SEC/PEI phase.
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In Dxe MMIO will be reassigned.
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Note: Fixed memory is not allocated in OS as MotherBoard/Device resource
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@param[in] PciCfgBase Pci Config Space Base
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@param[in] FixedBaseAddress Fixed Base Address for BAR0
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**/
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VOID
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SerialIoPciSetFixedMmio (
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IN UINT64 PciCfgBase,
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IN UINT32 FixedBaseAddress
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);
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/**
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Configures SerialIo to work on fixed address assignments
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Disables Pci Enumaration for given device in PSF
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@param[in] PciCfgBase Pci Config Space Base
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@param[in] FixedBaseAddress Fixed Base Address for BAR0
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@param[in] FixedPciCfgAddress Fixed Pci Config Space for BAR1
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@param[in] PciConfgCtrAddr Register offset for each Serial IO
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@param[in] PsfPort Psf Port data
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**/
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VOID
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SerialIoSetFixedMmio (
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IN UINT64 PciCfgBase,
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IN UINT32 FixedBaseAddress,
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IN UINT32 FixedPciCfgAddress,
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IN UINT16 PciConfgCtrAddr,
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IN PSF_PORT PsfPort
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);
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/**
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Enables Pci mode in PSF for given Serial IO
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@param[in] PciConfgCtrAddr Pci Config Register offset for Serial IO
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@param[in] PsfPort Psf Port data
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**/
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VOID
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SerialIoPciPsfEnable (
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IN UINT16 PciConfgCtrAddr,
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IN PSF_PORT PsfPort
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);
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/**
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Disables Base Address Register 1 (MMIO BAR1) in Serial Io device
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@param[in] PciConfgCtrAddr Pci Config Register offset for Serial IO
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@param[in] PsfPort Psf Port data
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**/
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VOID
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SerialIoBar1Disable (
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IN UINT16 PciConfgCtrAddr,
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IN PSF_PORT PsfPort
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);
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/**
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Configures SerialIo device PSF
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@param[in] PciConfgCtrAddr Pci Config Register offset for Serial IO
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@param[in] PsfPort Psf Port data
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**/
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VOID
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SerialIoPciEnable (
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IN UINT16 PciConfgCtrAddr,
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IN PSF_PORT PsfPort
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);
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/**
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Configures SerialIo devices interrupt pin and IRQ assignment
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@param[in] ConfigControlOffset Pci Config Register offset for Serial IO
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@param[in] InterruptPin Interrupt pin: INTA-INTD (see PCH_INT_PIN for reference)
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@param[in] Irq IRQ number
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**/
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VOID
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SerialIoInterruptSet (
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IN UINT16 ConfigControlOffset,
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IN UINT8 InterruptPin,
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IN UINT8 Irq
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);
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/**
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Enable SerialIo memory encoding
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@param[in] PciCfgBase Pci Config Offset
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@param[in] AssignTempBar Use temporary mem base address or not
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@param[in] Hidden Mode that determines access type
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@param[out] Base Base address
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@retval TRUE Base address was obtained successfully
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FALSE Failed to obtain Base Address Register address
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**/
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BOOLEAN
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SerialIoMmioEnable (
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IN UINT64 PciCfgBase,
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IN BOOLEAN AssignTempBar,
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IN BOOLEAN Hidden,
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OUT UINT64 *Base
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);
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/**
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Configures Serial IO Uart Controllers
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@param[in] SiPolicy Silicon policy
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@param[in] SerialIoConfig SerialIo Config Block
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**/
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VOID
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SerialIoUartInit (
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IN SI_POLICY_PPI *SiPolicy,
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IN PCH_SERIAL_IO_CONFIG *SerialIoConfig
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);
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/**
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Configures Serial IO Uart Function 0 Disabled Controllers
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@param[in] SiPolicy Silicon policy
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@param[in] SerialIoConfig SerialIo Config Block
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**/
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VOID
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SerialIoUartFunction0Disable (
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IN SI_POLICY_PPI *SiPolicy,
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IN PCH_SERIAL_IO_CONFIG *SerialIoConfig
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);
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/**
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Configures Serial IO Spi Controllers
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@param[in] SiPolicy Silicon policy
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@param[in] SerialIoConfig SerialIo Config Block
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**/
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VOID
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SerialIoSpiInit (
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IN SI_POLICY_PPI *SiPolicy,
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IN PCH_SERIAL_IO_CONFIG *SerialIoConfig
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);
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/**
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Configures Serial IO Spi Function 0 Disabled Controllers
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@param[in] SiPolicy Silicon policy
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@param[in] SerialIoConfig SerialIo Config Block
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**/
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VOID
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SerialIoSpiFunction0Disable (
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IN SI_POLICY_PPI *SiPolicy,
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IN PCH_SERIAL_IO_CONFIG *SerialIoConfig
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);
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/**
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Configures Serial IO I2c Controllers
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@param[in] SiPolicy Silicon policy
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@param[in] SerialIoConfig SerialIo Config Block
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**/
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VOID
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SerialIoI2cInit (
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IN SI_POLICY_PPI *SiPolicy,
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IN PCH_SERIAL_IO_CONFIG *SerialIoConfig
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);
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/**
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Configures Serial IO I2c Function 0 Disabled Controllers
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@param[in] SiPolicy Silicon policy
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@param[in] SerialIoConfig SerialIo Config Block
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**/
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VOID
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SerialIoI2cFunction0Disable (
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IN SI_POLICY_PPI *SiPolicy,
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IN PCH_SERIAL_IO_CONFIG *SerialIoConfig
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);
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/**
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Used to preserve current information about the device when it is configured in Pci mode in Pch Initialization.
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@param[in] PciCfgBase Pci Config Space Base
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@param[in/out] State Pointer to state settings container
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**/
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VOID
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SerialIoPciSave (
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IN UINT64 PciCfgBase,
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IN OUT SERIAL_IO_PCI_DEVICE_STATE *State
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);
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/**
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Used to restore device state after Pch Initialization.
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@param[in] PciCfgBase Pci Config Space Base
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@param[in] State Pointer to state settings container
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**/
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VOID
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SerialIoPciRestore (
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IN UINT64 PciCfgBase,
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IN SERIAL_IO_PCI_DEVICE_STATE *State
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);
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#endif //__PEI_SERIAL_IO_INIT_DDT_PRIVATE_LIB_H__
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