126 lines
5.3 KiB
C
126 lines
5.3 KiB
C
/** @file
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Memory Thermal Initialization Driver.
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;******************************************************************************
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;* Copyright (c) 2015, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#include <Uefi.h>
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#include <ChipsetSetupConfig.h>
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#include <SaAccess.h>
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#include <Source/Include/MrcRegisters/Msa.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiRuntimeServicesTableLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PciLib.h>
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#include <Library/DxeInsydeChipsetLib.h>
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EFI_STATUS
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MemoryThermalEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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SA_SETUP *SaSetup;
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UINT16 Data16;
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UINT32 Data32;
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Status = EFI_SUCCESS;
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Data16 = 0;
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Data32 = 0;
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SaSetup = NULL;
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SaSetup = AllocateZeroPool (sizeof (SA_SETUP));
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if (SaSetup == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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Status = GetChipsetSaSetupVariableDxe (SaSetup, sizeof (SA_SETUP));
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if (EFI_ERROR (Status)) {
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FreePool (SaSetup);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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Data32 = (BIT0 << PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_OFF);
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if (SaSetup->EnableExtts) {
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Data32 |= (BIT0 << PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_OFF);
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}
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if (SaSetup->EnableCltm) {
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Data32 |= (BIT0 << PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_OFF);
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}
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if (SaSetup->EnableOltm) {
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Data32 |= (BIT0 << PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_OFF);
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}
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McMmio32Or (PCU_CR_DDR_PTM_CTL_PCU_REG, Data32);
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Data16 = (SaSetup->WarmThresholdCh0Dimm0 << PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_OFF) |
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(SaSetup->WarmThresholdCh0Dimm1 << PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_OFF);
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McMmio16AndThenOr(PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_REG, 0,Data16);
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Data16 = (SaSetup->WarmThresholdCh1Dimm0 << PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_OFF) |
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(SaSetup->WarmThresholdCh1Dimm1 << PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_OFF);
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McMmio16AndThenOr(PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_REG, 0,Data16);
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Data16 = (SaSetup->HotThresholdCh0Dimm0 << PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_OFF) |
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(SaSetup->HotThresholdCh0Dimm1 << PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_OFF);
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McMmio16AndThenOr(PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_REG, 0,Data16);
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Data16 = (SaSetup->HotThresholdCh1Dimm0 << PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_OFF) |
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(SaSetup->HotThresholdCh1Dimm1 << PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_OFF);
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McMmio16AndThenOr (PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_REG, 0, Data16);
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Data16 = (SaSetup->WarmBudgetCh0Dimm0 << PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_OFF) |
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(SaSetup->WarmBudgetCh0Dimm1 << PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_OFF);
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McMmio16AndThenOr (PCU_CR_DDR_WARM_BUDGET_CH0_PCU_REG, 0, Data16);
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Data16 = (SaSetup->WarmBudgetCh1Dimm0 << PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_OFF) |
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(SaSetup->WarmBudgetCh1Dimm1 << PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_OFF);
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McMmio16AndThenOr (PCU_CR_DDR_WARM_BUDGET_CH1_PCU_REG, 0, Data16);
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Data16 = (SaSetup->HotBudgetCh0Dimm0 << PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_OFF) |
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(SaSetup->HotBudgetCh0Dimm1 << PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_OFF);
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McMmio16AndThenOr (PCU_CR_DDR_HOT_BUDGET_CH0_PCU_REG, 0, Data16);
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Data16 = (SaSetup->HotBudgetCh1Dimm0 << PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_OFF) |
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(SaSetup->HotBudgetCh1Dimm1 << PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_OFF);
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McMmio16AndThenOr (PCU_CR_DDR_HOT_BUDGET_CH1_PCU_REG, 0, Data16);
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// gino: new RC already remove
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Data32 = (SaSetup->RaplLim1Pwr & PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_MSK) |
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(SaSetup->RaplLim1Ena << PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_OFF) |
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(SaSetup->RaplLim1WindX << PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_OFF) |
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(SaSetup->RaplLim1WindY << PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_OFF);
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// Data32 = (SaSetup->RaplLim1Ena << PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_OFF) |
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// (SaSetup->RaplLim1WindX << PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_OFF) |
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// (SaSetup->RaplLim1WindY << PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_OFF);
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McMmio32Or (PCU_CR_DDR_RAPL_LIMIT_PCU_REG, Data32);
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Data32 = (SaSetup->RaplLim2Pwr & PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_MSK) |
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(SaSetup->RaplLim2Ena << (PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_OFF - 32)) |
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(SaSetup->RaplLim2WindX << (PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_OFF - 32)) |
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(SaSetup->RaplLim2WindY << (PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_OFF - 32));
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McMmio32Or (PCU_CR_DDR_RAPL_LIMIT_PCU_REG + 4, Data32);
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Data32 = McMmio32(PCU_CR_DDR_RAPL_LIMIT_PCU_REG + 4);
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Data32 |= (SaSetup->RaplLim2Lock << (PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_OFF - 32));
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McMmio32Or (PCU_CR_DDR_RAPL_LIMIT_PCU_REG + 4, Data32);
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gBS->FreePool (SaSetup);
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return EFI_SUCCESS;
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}
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