141 lines
5.3 KiB
C
141 lines
5.3 KiB
C
/** @file
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;******************************************************************************
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;* Copyright (c) 2014, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#ifndef _VBT_ACCESS_H_
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#define _VBT_ACCESS_H_
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#include "VBTRegs.h"
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#define VBTAddress( BaseAddr, Register ) \
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( ( UINTN )( BaseAddr ) + ( UINTN )( Register ) )
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#define VBTPtr( GRANULARITY, BaseAddr, Register ) \
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( ( volatile GRANULARITY * )VBTAddress ( BaseAddr, Register ) )
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#define VBT( GRANULARITY, BaseAddr, Register ) \
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( *VBTPtr ( GRANULARITY, BaseAddr, Register ) )
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#define VBTUpdateChecksum( BaseAddr, Register, Data ) \
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( VBT ( UINT8, BaseAddr, R_VBT_CHECKSUM ) = ( UINT8 )( VBT ( UINT8, BaseAddr, R_VBT_CHECKSUM ) + VBT ( UINT8, BaseAddr, Register ) - ( Data ) ) )
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#define VBT8UpdateChecksum( BaseAddr, Register, Data ) \
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{ \
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VBTUpdateChecksum ( BaseAddr, ( Register + 0 ), ( UINT8 )( Data >> 0 ) ); \
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}
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#define VBT8Read( BaseAddr, Register ) \
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( VBT ( UINT8, BaseAddr, Register ) )
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#define VBT8Write( BaseAddr, Register, Data ) \
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{ \
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VBT8UpdateChecksum ( BaseAddr, Register, Data ); \
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VBT ( UINT8, BaseAddr, Register ) = ( UINT8 )( Data ); \
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}
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#define VBT8And( BaseAddr, Register, AndData ) \
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VBT8Write ( \
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BaseAddr, \
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Register, \
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( VBT8Read ( BaseAddr, Register ) & AndData ) \
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)
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#define VBT8Or( BaseAddr, Register, OrData ) \
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VBT8Write ( \
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BaseAddr, \
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Register, \
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( VBT8Read ( BaseAddr, Register ) | OrData ) \
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)
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#define VBT8AndThenOr( BaseAddr, Register, AndData, OrData ) \
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VBT8Write ( \
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BaseAddr, \
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Register, \
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( ( VBT8Read ( BaseAddr, Register ) & AndData ) | OrData ) \
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)
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#define VBT16UpdateChecksum( BaseAddr, Register, Data ) \
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{ \
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VBTUpdateChecksum ( BaseAddr, ( Register + 0 ), ( UINT8 )( Data >> 0 ) ); \
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VBTUpdateChecksum ( BaseAddr, ( Register + 1 ), ( UINT8 )( Data >> 8 ) ); \
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}
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#define VBT16Read( BaseAddr, Register ) \
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( VBT ( UINT16, BaseAddr, Register ) )
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#define VBT16Write( BaseAddr, Register, Data ) \
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{ \
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VBT16UpdateChecksum ( BaseAddr, Register, Data ); \
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VBT ( UINT16, BaseAddr, Register ) = ( UINT16 )( Data ); \
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}
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#define VBT16And( BaseAddr, Register, AndData ) \
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VBT16Write ( \
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BaseAddr, \
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Register, \
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( VBT16Read ( BaseAddr, Register ) & AndData ) \
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)
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#define VBT16Or( BaseAddr, Register, OrData ) \
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VBT16Write ( \
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BaseAddr, \
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Register, \
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( VBT16Read ( BaseAddr, Register ) | OrData ) \
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)
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#define VBT16AndThenOr( BaseAddr, Register, AndData, OrData ) \
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VBT16Write ( \
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BaseAddr, \
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Register, \
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( ( VBT16Read ( BaseAddr, Register ) & AndData ) | OrData ) \
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)
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#define VBT32UpdateChecksum( BaseAddr, Register, Data ) \
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{ \
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VBTUpdateChecksum ( BaseAddr, ( Register + 0 ), ( UINT8 )( Data >> 0 ) ); \
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VBTUpdateChecksum ( BaseAddr, ( Register + 1 ), ( UINT8 )( Data >> 8 ) ); \
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VBTUpdateChecksum ( BaseAddr, ( Register + 2 ), ( UINT8 )( Data >> 16 ) ); \
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VBTUpdateChecksum ( BaseAddr, ( Register + 3 ), ( UINT8 )( Data >> 24 ) ); \
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}
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#define VBT32Read( BaseAddr, Register ) \
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( VBT ( UINT32, BaseAddr, Register ) )
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#define VBT32Write( BaseAddr, Register, Data ) \
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{ \
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VBT32UpdateChecksum ( BaseAddr, Register, Data ); \
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VBT ( UINT32, BaseAddr, Register ) = ( UINT32 )( Data ); \
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}
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#define VBT32And( BaseAddr, Register, AndData ) \
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VBT32Write ( \
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BaseAddr, \
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Register, \
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( VBT32Read ( BaseAddr, Register ) & AndData ) \
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)
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#define VBT32Or( BaseAddr, Register, OrData ) \
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VBT32Write ( \
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BaseAddr, \
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Register, \
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( VBT32Read ( BaseAddr, Register ) | OrData ) \
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)
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#define VBT32AndThenOr( BaseAddr, Register, AndData, OrData ) \
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VBT32Write ( \
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BaseAddr, \
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Register, \
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( ( VBT32Read ( BaseAddr, Register ) & AndData ) | OrData ) \
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)
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#endif
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