108 lines
5.3 KiB
C
108 lines
5.3 KiB
C
/** @file
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This file is SampleCode of the library for Intel PCH PEI Policy initialization in post-memory.
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Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <FspEas.h>
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#include <FspsUpd.h>
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#include <Library/PcdLib.h>
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#include <Pins/GpioPinsVer2Lp.h>
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#include <Library/PchInfoLib.h>
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#include <TcssInfo.h>
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#ifndef MAX_IOM_AUX_BIAS_COUNT
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#define MAX_IOM_AUX_BIAS_COUNT 6 // This define by SKU 4/6
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#endif
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IOM_AUX_ORI_PAD_CONFIG mIomAuxNullTable[MAX_IOM_AUX_BIAS_COUNT] = {
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// Pull UP GPIO Pin, Pull Down GPIO pin
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{0, 0}, // Port 0
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{0, 0}, // Port 1
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{0, 0}, // Port 2
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{0, 0}, // Port 3
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{0, 0}, // Port 4
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{0, 0}, // Port 5
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};
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/**
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Performs FSP PCH PEI Policy initialization.
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@param[in][out] FspsUpd Pointer to FSP UPD Data.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
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EFI_STATUS
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EFIAPI
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PeiFspPchPolicyUpdatePostMem (
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IN OUT FSPS_UPD *FspsUpd
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)
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{
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UINT32 PortIndex;
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FspsUpd->FspsConfig.Usb2OverCurrentPin[0] = PcdGet8 (PcdUsb20OverCurrentPinPort0);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[1] = PcdGet8 (PcdUsb20OverCurrentPinPort1);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[2] = PcdGet8 (PcdUsb20OverCurrentPinPort2);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[3] = PcdGet8 (PcdUsb20OverCurrentPinPort3);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[4] = PcdGet8 (PcdUsb20OverCurrentPinPort4);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[5] = PcdGet8 (PcdUsb20OverCurrentPinPort5);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[6] = PcdGet8 (PcdUsb20OverCurrentPinPort6);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[7] = PcdGet8 (PcdUsb20OverCurrentPinPort7);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[8] = PcdGet8 (PcdUsb20OverCurrentPinPort8);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[9] = PcdGet8 (PcdUsb20OverCurrentPinPort9);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[10] = PcdGet8 (PcdUsb20OverCurrentPinPort10);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[11] = PcdGet8 (PcdUsb20OverCurrentPinPort11);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[12] = PcdGet8 (PcdUsb20OverCurrentPinPort12);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[13] = PcdGet8 (PcdUsb20OverCurrentPinPort13);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[14] = PcdGet8 (PcdUsb20OverCurrentPinPort14);
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FspsUpd->FspsConfig.Usb2OverCurrentPin[15] = PcdGet8 (PcdUsb20OverCurrentPinPort15);
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FspsUpd->FspsConfig.SataPortsEnable[0] = PcdGet8 (PcdSataPortsEnable0);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[0] = PcdGet8 (PcdUsb30OverCurrentPinPort0);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[1] = PcdGet8 (PcdUsb30OverCurrentPinPort1);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[2] = PcdGet8 (PcdUsb30OverCurrentPinPort2);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[3] = PcdGet8 (PcdUsb30OverCurrentPinPort3);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[4] = PcdGet8 (PcdUsb30OverCurrentPinPort4);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[5] = PcdGet8 (PcdUsb30OverCurrentPinPort5);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[6] = PcdGet8 (PcdUsb30OverCurrentPinPort6);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[7] = PcdGet8 (PcdUsb30OverCurrentPinPort7);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[8] = PcdGet8 (PcdUsb30OverCurrentPinPort8);
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FspsUpd->FspsConfig.Usb3OverCurrentPin[9] = PcdGet8 (PcdUsb30OverCurrentPinPort9);
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for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
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FspsUpd->FspsConfig.PortUsb30Enable[PortIndex] = TRUE; // Default Enable all Port
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}
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FspsUpd->FspsConfig.SerialIoUartRxPinMuxPolicy[0] = GPIO_VER2_LP_MUXING_SERIALIO_UART0_RXD_GPP_F1;
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FspsUpd->FspsConfig.SerialIoUartTxPinMuxPolicy[0] = GPIO_VER2_LP_MUXING_SERIALIO_UART0_TXD_GPP_F2;
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FspsUpd->FspsConfig.SerialIoUartRtsPinMuxPolicy[0] = GPIO_VER2_LP_MUXING_SERIALIO_UART0_RTS_GPP_F0;
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FspsUpd->FspsConfig.SerialIoUartCtsPinMuxPolicy[0] = GPIO_VER2_LP_MUXING_SERIALIO_UART0_CTS_GPP_F3;
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FspsUpd->FspsConfig.PchHdaAudioLinkDmic0ClkAPinMux = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6;
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FspsUpd->FspsConfig.PchHdaAudioLinkDmic0ClkBPinMux = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2;
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FspsUpd->FspsConfig.PchHdaAudioLinkDmic0DataPinMux = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7;
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FspsUpd->FspsConfig.PchHdaAudioLinkDmic1ClkAPinMux = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4;
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FspsUpd->FspsConfig.PchHdaAudioLinkDmic1ClkBPinMux = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3;
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FspsUpd->FspsConfig.PchHdaAudioLinkDmic1DataPinMux = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
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for (PortIndex = 0; PortIndex < TCSS_MAX_USB3_PORTS; PortIndex++) {
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FspsUpd->FspsConfig.IomTypeCPortPadCfg[(PortIndex * 2)] = mIomAuxNullTable[PortIndex].GpioPullN;
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FspsUpd->FspsConfig.IomTypeCPortPadCfg[(PortIndex * 2) + 1] = mIomAuxNullTable[PortIndex].GpioPullP;
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}
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return EFI_SUCCESS;
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}
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