1146 lines
94 KiB
C
1146 lines
94 KiB
C
//
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// Automatically generated by GenNvs ver 2.4.2
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// Please DO NOT modify !!!
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//
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/** @file
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ACPI DSDT table
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2011 - 2017 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification
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**/
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// Define a Global region of ACPI NVS Region that may be used for any
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// type of implementation. The starting offset and size will be fixed
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// up by the System BIOS during POST. Note that the Size must be a word
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// in size to be fixed up correctly.
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#ifndef _PLATFORM_NVS_AREA_DEF_H_
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#define _PLATFORM_NVS_AREA_DEF_H_
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#pragma pack (push,1)
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typedef struct {
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//
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// Miscellaneous Dynamic Registers:
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//
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UINT16 OperatingSystem; ///< Offset 0 Operating System
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UINT8 SmiFunction; ///< Offset 2 SMI Function Call (ASL to SMI via I/O Trap)
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UINT8 SmiParameter0; ///< Offset 3 SMIF - Parameter 0
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UINT8 SmiParameter1; ///< Offset 4 SMIF - Parameter 1
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UINT8 SciFunction; ///< Offset 5 SCI Function Call (SMI to ASL via _L00)
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UINT8 SciParameter0; ///< Offset 6 SCIF - Parameter 0
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UINT8 SciParameter1; ///< Offset 7 SCIF - Parameter 1
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UINT8 GlobalLock; ///< Offset 8 Global Lock Function Call (EC Communication)
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UINT8 LockParameter0; ///< Offset 9 LCKF - Parameter 0
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UINT8 LockParameter1; ///< Offset 10 LCKF - Parameter 1
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UINT8 PowerState; ///< Offset 11 Power State (AC Mode = 1)
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UINT8 DebugState; ///< Offset 12 Debug State
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//
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// Thermal Policy Registers:
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//
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UINT8 EnableThermalKSC; ///< Offset 13 Enable Thermal Offset for KSC
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UINT8 Ac1TripPoint; ///< Offset 14 Active Trip Point 1
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UINT8 Ac0TripPoint; ///< Offset 15 Active Trip Point
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UINT8 PassiveThermalTripPoint; ///< Offset 16 Passive Trip Point
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UINT8 PassiveTc1Value; ///< Offset 17 Passive Trip Point TC1 Value
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UINT8 PassiveTc2Value; ///< Offset 18 Passive Trip Point TC2 Value
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UINT8 PassiveTspValue; ///< Offset 19 Passive Trip Point TSP Value
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UINT8 CriticalThermalTripPoint; ///< Offset 20 Critical Trip Point
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//
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// Revision Field:
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//
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UINT8 Revision; ///< Offset 25 Revison of GlobalNvsArea
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//
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// CPU Identification Registers:
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//
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UINT8 ApicEnable; ///< Offset 26 APIC Enabled by SBIOS (APIC Enabled = 1)
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UINT8 ThreadCount; ///< Offset 27 Number of Enabled Threads
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UINT8 CurentPdcState0; ///< Offset 28 PDC Settings, Processor 0
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UINT8 CurentPdcState1; ///< Offset 29 PDC Settings, Processor 1
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UINT8 MaximumPpcState; ///< Offset 30 Maximum PPC state
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UINT32 PpmFlags; ///< Offset 31 PPM Flags (Same as CFGD)
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UINT8 C6C7Latency; ///< Offset 35 C6/C7 Entry/Exit latency
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//
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// SIO Configuration Registers:
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//
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UINT8 DockedSioPresent; ///< Offset 36 National SIO Present
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UINT8 DockComA; ///< Offset 37 COM A Port
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UINT8 DockComB; ///< Offset 38 COM B Port
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UINT8 DockLpt; ///< Offset 39 LPT Port
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UINT8 DockFdc; ///< Offset 40 FDC Port
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UINT8 OnboardCom; ///< Offset 41 SMSC Com Port
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UINT8 OnboardComCir; ///< Offset 42 SMSC Com CIR Port
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UINT8 SMSC1007; ///< Offset 43 SMSC1007 SIO Present
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UINT8 WPCN381U; ///< Offset 44 WPCN381U SIO Present
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UINT8 SMSC1000; ///< Offset 45 SMSC1000 SIO Present
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//
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// Extended Mobile Access Values
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//
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UINT8 EmaEnable; ///< Offset 46 EMA Enable
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UINT16 EmaPointer; ///< Offset 47 EMA Pointer
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UINT16 EmaLength; ///< Offset 49 EMA Length
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//
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// MEF Registers:
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//
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UINT8 MefEnable; ///< Offset 51 MEF Enable
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//
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// PCIe Dock Status:
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//
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UINT8 PcieDockStatus; ///< Offset 52 PCIe Dock Status
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//
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// TPM Registers
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//
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UINT8 MorData; ///< Offset 53 Memory Overwrite Request Data
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UINT8 TcgParamter; ///< Offset 54 Used for save the Mor and/or physical presence paramter
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UINT32 PPResponse; ///< Offset 55 Physical Presence request operation response
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UINT8 PPRequest; ///< Offset 59 Physical Presence request operation
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UINT8 LastPPRequest; ///< Offset 60 Last Physical Presence request operation
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//
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// SATA Registers:
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//
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UINT8 IdeMode; ///< Offset 61 IDE Mode (Compatible\Enhanced)
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//
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// Board Id
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//
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UINT8 PlatformId; ///< Offset 62 Platform id
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UINT8 BoardType; ///< Offset 63 Board Type
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//
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// PCIe Hot Plug
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//
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UINT8 PcieOSCControl; ///< Offset 64 PCIE OSC Control
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UINT8 NativePCIESupport; ///< Offset 65 Native PCIE Setup Value
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//
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// USB Sideband Deferring Support
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//
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UINT8 HostAlertVector1; ///< Offset 66 USB Sideband Deferring GPE Vector (HOST_ALERT#1)
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UINT8 HostAlertVector2; ///< Offset 67 USB Sideband Deferring GPE Vector (HOST_ALERT#2)
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//
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// Embedded Controller Availability Flag.
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//
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UINT8 EcAvailable; ///< Offset 68 Embedded Controller Availability Flag.
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//
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// Global Variables
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//
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UINT8 DisplaySupportFlag; ///< Offset 69 _DOS Display Support Flag.
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UINT8 InterruptModeFlag; ///< Offset 70 Global IOAPIC/8259 Interrupt Mode Flag.
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UINT8 CoolingTypeFlag; ///< Offset 71 Global Cooling Type Flag.
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UINT8 L01Counter; ///< Offset 72 Global L01 Counter.
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UINT8 VirtualFan0Status; ///< Offset 73 Virtual Fan0 Status.
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UINT8 VirtualFan1Status; ///< Offset 74 Virtual Fan1 Status.
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UINT8 VirtualFan2Status; ///< Offset 75 Virtual Fan2 Status.
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UINT8 VirtualFan3Status; ///< Offset 76 Virtual Fan3 Status.
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UINT8 VirtualFan4Status; ///< Offset 77 Virtual Fan4 Status.
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UINT8 VirtualFan5Status; ///< Offset 78 Virtual Fan5 Status.
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UINT8 VirtualFan6Status; ///< Offset 79 Virtual Fan6 Status.
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UINT8 VirtualFan7Status; ///< Offset 80 Virtual Fan7 Status.
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UINT8 VirtualFan8Status; ///< Offset 81 Virtual Fan8 Status.
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UINT8 VirtualFan9Status; ///< Offset 82 Virtual Fan9 Status.
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//
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// Thermal
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//
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UINT8 ActiveThermalTripPointSA; ///< Offset 83 Active Trip Point for MCH
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UINT8 PassiveThermalTripPointSA; ///< Offset 84 Passive Trip Point for MCH
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UINT32 PlatformCpuId; ///< Offset 85 CPUID Feature Information [EAX]
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UINT32 TBARB; ///< Offset 89 Reserved for Thermal Base Low Address for BIOS
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UINT32 TBARBH; ///< Offset 93 Reserved for Thermal Base High Address for BIOS
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UINT8 TsOnDimmEnabled; ///< Offset 97 TS-on-DIMM is chosen in SETUP and present on the DIMM
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//
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// Board info
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//
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UINT8 PlatformFlavor; ///< Offset 98 Platform Flavor
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UINT8 BoardRev; ///< Offset 99 Board Rev
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//
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// Package temperature
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//
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UINT8 PeciAccessMethod; ///< Offset 102 Peci Access Method
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UINT8 Ac0FanSpeed; ///< Offset 103 _AC0 Fan Speed
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UINT8 Ac1FanSpeed; ///< Offset 104 _AC1 Fan Speed
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//
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// XTU 3.0 Specification
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//
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UINT32 XTUBaseAddress; ///< Offset 107 XTU Continous structure Base Address
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UINT32 XTUSize; ///< Offset 111 XMP Size
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UINT32 XMPBaseAddress; ///< Offset 115 XMP Base Address
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UINT8 DDRReferenceFreq; ///< Offset 119 DDR Reference Frequency
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UINT8 Rtd3Support; ///< Offset 120 Runtime D3 support.
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UINT8 Rtd3P0dl; ///< Offset 121 User selctable Delay for Device D0 transition.
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UINT8 Rtd3P3dl; ///< Offset 122 User selctable Delay for Device D3 transition.
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//
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// DPTF Devices and trip points
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//
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UINT8 EnableDptf; ///< Offset 123 EnableDptf
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UINT16 EnableDCFG; ///< Offset 124 EnableDCFG
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UINT8 EnableSaDevice; ///< Offset 126 EnableSaDevice
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UINT8 CriticalThermalTripPointSA; ///< Offset 127 CriticalThermalTripPointSa
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UINT8 HotThermalTripPointSA; ///< Offset 128 HotThermalTripPointSa
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UINT8 ThermalSamplingPeriodSA; ///< Offset 129 ThermalSamplingPeriodSA
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//
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// DPTF Policies
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//
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UINT8 EnableCtdpPolicy; ///< Offset 130 EnableCtdpPolicy
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//
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// DPPM Devices and trip points
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//
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UINT8 EnableFan1Device; ///< Offset 131 EnableFan1Device
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UINT8 EnableAmbientDevice; ///< Offset 132 EnableAmbientDevice
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UINT8 ActiveThermalTripPointAmbient; ///< Offset 133 ActiveThermalTripPointAmbient
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UINT8 PassiveThermalTripPointAmbient; ///< Offset 134 PassiveThermalTripPointAmbient
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UINT8 CriticalThermalTripPointAmbient; ///< Offset 135 CriticalThermalTripPointAmbient
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UINT8 HotThermalTripPointAmbient; ///< Offset 136 HotThermalTripPointAmbient
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UINT8 EnableSkinDevice; ///< Offset 137 EnableSkinDevice
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UINT8 ActiveThermalTripPointSkin; ///< Offset 138 ActiveThermalTripPointSkin
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UINT8 PassiveThermalTripPointSkin; ///< Offset 139 PassiveThermalTripPointSkin
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UINT8 CriticalThermalTripPointSkin; ///< Offset 140 CriticalThermalTripPointSkin
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UINT8 HotThermalTripPointSkin; ///< Offset 141 HotThermalTripPointSkin
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UINT8 EnableExhaustFanDevice; ///< Offset 142 EnableExhaustFanDevice
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UINT8 ActiveThermalTripPointExhaustFan; ///< Offset 143 ActiveThermalTripPointExhaustFan
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UINT8 PassiveThermalTripPointExhaustFan; ///< Offset 144 PassiveThermalTripPointExhaustFan
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UINT8 CriticalThermalTripPointExhaustFan; ///< Offset 145 CriticalThermalTripPointExhaustFan
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UINT8 HotThermalTripPointExhaustFan; ///< Offset 146 HotThermalTripPointExhaustFan
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UINT8 EnableVRDevice; ///< Offset 147 EnableVRDevice
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UINT8 ActiveThermalTripPointVR; ///< Offset 148 ActiveThermalTripPointVR
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UINT8 PassiveThermalTripPointVR; ///< Offset 149 PassiveThermalTripPointVR
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UINT8 CriticalThermalTripPointVR; ///< Offset 150 CriticalThermalTripPointVR
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UINT8 HotThermalTripPointVR; ///< Offset 151 HotThermalTripPointVR
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//
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// DPPM Policies
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//
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UINT8 EnableActivePolicy; ///< Offset 152 EnableActivePolicy
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UINT8 EnablePassivePolicy; ///< Offset 153 EnablePassivePolicy
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UINT8 EnableCriticalPolicy; ///< Offset 154 EnableCriticalPolicy
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UINT8 EnablePIDPolicy; ///< Offset 155 EnablePIDPolicy
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UINT8 TrtRevision; ///< Offset 156 TrtRevision
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//
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// CLPO (Current Logical Processor Off lining Setting)
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//
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UINT8 LPOEnable; ///< Offset 157 LPOEnable
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UINT8 LPOStartPState; ///< Offset 158 LPOStartPState
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UINT8 LPOStepSize; ///< Offset 159 LPOStepSize
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UINT8 LPOPowerControlSetting; ///< Offset 160 LPOPowerControlSetting
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UINT8 LPOPerformanceControlSetting; ///< Offset 161 LPOPerformanceControlSetting
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//
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// Miscellaneous DPTF
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//
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UINT32 PpccStepSize; ///< Offset 162 PPCC Step Size
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UINT8 EnableDisplayParticipant; ///< Offset 166 EnableDisplayParticipant
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//
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// BIOS Guard
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//
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UINT64 BiosGuardMemAddress; ///< Offset 167 BIOS Guard Memory Address for Tool Interface
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UINT8 BiosGuardMemSize; ///< Offset 175 BIOS Guard Memory Size for Tool Interface
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UINT16 BiosGuardIoTrapAddress; ///< Offset 176 BIOS Guard IoTrap Address for Tool Interface
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//
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// Comms Hub
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//
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UINT8 CommsHubEnable; ///< Offset 179 Comms Hub Enable/Disable
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UINT8 LowPowerS0Idle; ///< Offset 180 Low Power S0 Idle Enable
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//
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// BIOS only version of Config TDP
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//
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UINT8 ConfigTdpBios; ///< Offset 181 enable/disable BIOS only version of Config TDP
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UINT8 DockSmi; ///< Offset 182 Dock SMI number
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//
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// LPC SIO configuration
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//
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UINT16 LpcSioPort1; ///< Offset 183 SIO config port 1
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UINT16 LpcSioPort2; ///< Offset 185 SIO config port 2
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UINT16 LpcSioPmeBar; ///< Offset 187 SIO PME Base Address
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UINT8 Reserved0[311]; ///< Offset 189:499
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UINT8 EnableWrlsParticipant; ///< Offset 500 EnableWrlsParticipant
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UINT8 ActiveThermalTripPointWrls; ///< Offset 501 ActiveThermalTripPointWrls
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UINT8 PassiveThermalTripPointWrls; ///< Offset 502 PassiveThermalTripPointWrls
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UINT8 CriticalThermalTripPointWrls; ///< Offset 503 CriticalThermalTripPointWrls
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UINT8 HotThermalTripPointWrls; ///< Offset 504 HotThermalTripPointWrls
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UINT8 EnablePowerParticipant; ///< Offset 505 EnablePowerParticipant
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UINT16 DPTFRsvd0; ///< Offset 506 DPTFRsvd0
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UINT16 PowerParticipantPollingRate; ///< Offset 508 PowerParticipantPollingRate
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UINT8 EnablePowerBossPolicy; ///< Offset 510 EnablePowerBossPolicy
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UINT8 EnableVSPolicy; ///< Offset 511 EnableVSPolicy
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UINT8 EnableRFIMPolicy; ///< Offset 512 RFI Mitigation
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UINT8 Reserved1[2]; ///< Offset 513:514
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UINT8 UsbPowerResourceTest; ///< Offset 515 RTD3 USB Power Resource config
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UINT8 Rtd3I2C0SensorHub; ///< Offset 516 RTD3 support for I2C0 SH
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UINT8 VirtualGpioButtonSxBitmask; ///< Offset 517 Virtual GPIO button Notify Sleep State Change
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UINT8 IuerButtonEnable; ///< Offset 518 IUER Button Enable
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UINT8 IuerConvertibleEnable; ///< Offset 519 IUER Convertible Enable
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UINT8 IuerDockEnable; ///< Offset 520 IUER Dock Enable
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UINT8 CSNotifyEC; ///< Offset 521 EC Notification of Low Power S0 Idle State
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UINT16 Rtd3AudioDelay; ///< Offset 522 RTD3 Audio Codec device delay
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UINT16 Rtd3SensorHub; ///< Offset 524 RTD3 SensorHub delay time after applying power to device
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UINT16 Rtd3TouchPanelDelay; ///< Offset 526 RTD3 TouchPanel delay time after applying power to device
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UINT16 Rtd3TouchPadDelay; ///< Offset 528 RTD3 TouchPad delay time after applying power to device
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UINT16 VRRampUpDelay; ///< Offset 530 VR Ramp up delay
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UINT8 PstateCapping; ///< Offset 532 P-state Capping
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UINT16 Rtd3I2C0ControllerPS0Delay; ///< Offset 533 Delay in _PS0 after powering up I2C0 Controller
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UINT16 Rtd3I2C1ControllerPS0Delay; ///< Offset 535 Delay in _PS0 after powering up I2C1 Controller
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UINT16 Rtd3Config0; ///< Offset 537 RTD3 Config Setting0(BIT0:ZPODD, BIT1:Reserved, BIT2:PCIe NVMe, Bit4:SKL SDS SIP I2C Touch, BIT6:Card Reader, BIT7:WWAN)
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UINT16 Rtd3Config1; ///< Offset 539 RTD3 Config Setting1(BIT0:Sata Port0, BIT1:Sata Port1, BIT2:Sata Port2, BIT3:Sata Port3)
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UINT8 CSDebugLightEC; ///< Offset 541 EC Debug Light (CAPS LOCK) for when in Low Power S0 Idle State
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UINT8 Ps2MouseEnable; ///< Offset 542 Ps2 Mouse Enable
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UINT8 Ps2KbMsEnable; ///< Offset 543 Ps2 Keyboard and Mouse Enable
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UINT8 DiscreteWifiRtd3ColdSupport; ///< Offset 544 Enable RTD3 Cold Support for Wifi
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UINT8 DiscreteWigigRtd3ColdSupport; ///< Offset 545 Enable RTD3 Cold Support for Wigig
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UINT8 DiscreteWwanRtd3ColdSupport; ///< Offset 546 Enable RTD3 Cold Support for WWAN
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UINT16 SSH0; ///< Offset 547 SSCN-HIGH for I2C0
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UINT16 SSL0; ///< Offset 549 SSCN-LOW for I2C0
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UINT16 SSD0; ///< Offset 551 SSCN-HOLD for I2C0
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UINT16 FMH0; ///< Offset 553 FMCN-HIGH for I2C0
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UINT16 FML0; ///< Offset 555 FMCN-LOW for I2C0
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UINT16 FMD0; ///< Offset 557 FMCN-HOLD for I2C0
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UINT16 FPH0; ///< Offset 559 FPCN-HIGH for I2C0
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UINT16 FPL0; ///< Offset 561 FPCN-LOW for I2C0
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UINT16 FPD0; ///< Offset 563 FPCN-HOLD for I2C0
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UINT16 HSH0; ///< Offset 565 HSCN-HIGH for I2C0
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UINT16 HSL0; ///< Offset 567 HSCN-LOW for I2C0
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UINT16 HSD0; ///< Offset 569 HSCN-HOLD for I2C0
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UINT8 Reserved2[2]; ///< Offset 571:572
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UINT16 SSH1; ///< Offset 573 SSCN-HIGH for I2C1
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UINT16 SSL1; ///< Offset 575 SSCN-LOW for I2C1
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UINT16 SSD1; ///< Offset 577 SSCN-HOLD for I2C1
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UINT16 FMH1; ///< Offset 579 FMCN-HIGH for I2C1
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UINT16 FML1; ///< Offset 581 FMCN-LOW for I2C1
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UINT16 FMD1; ///< Offset 583 FMCN-HOLD for I2C1
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UINT16 FPH1; ///< Offset 585 FPCN-HIGH for I2C1
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UINT16 FPL1; ///< Offset 587 FPCN-LOW for I2C1
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UINT16 FPD1; ///< Offset 589 FPCN-HOLD for I2C1
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UINT16 HSH1; ///< Offset 591 HSCN-HIGH for I2C1
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UINT16 HSL1; ///< Offset 593 HSCN-LOW for I2C1
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UINT16 HSD1; ///< Offset 595 HSCN-HOLD for I2C1
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UINT8 Reserved3[1]; ///< Offset 597:597
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UINT16 SSH2; ///< Offset 598 SSCN-HIGH for I2C2
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UINT16 SSL2; ///< Offset 600 SSCN-LOW for I2C2
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UINT16 SSD2; ///< Offset 602 SSCN-HOLD for I2C2
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UINT16 FMH2; ///< Offset 604 FMCN-HIGH for I2C2
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UINT16 FML2; ///< Offset 606 FMCN-LOW for I2C2
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UINT16 FMD2; ///< Offset 608 FMCN-HOLD for I2C2
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UINT16 FPH2; ///< Offset 610 FPCN-HIGH for I2C2
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UINT16 FPL2; ///< Offset 612 FPCN-LOW for I2C2
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UINT16 FPD2; ///< Offset 614 FPCN-HOLD for I2C2
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UINT16 HSH2; ///< Offset 616 HSCN-HIGH for I2C2
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UINT16 HSL2; ///< Offset 618 HSCN-LOW for I2C2
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UINT16 HSD2; ///< Offset 620 HSCN-HOLD for I2C2
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UINT8 Reserved4[1]; ///< Offset 622:622
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UINT16 SSH3; ///< Offset 623 SSCN-HIGH for I2C3
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UINT16 SSL3; ///< Offset 625 SSCN-LOW for I2C3
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UINT16 SSD3; ///< Offset 627 SSCN-HOLD for I2C3
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UINT16 FMH3; ///< Offset 629 FMCN-HIGH for I2C3
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UINT16 FML3; ///< Offset 631 FMCN-LOW for I2C3
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UINT16 FMD3; ///< Offset 633 FMCN-HOLD for I2C3
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UINT16 FPH3; ///< Offset 635 FPCN-HIGH for I2C3
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UINT16 FPL3; ///< Offset 637 FPCN-LOW for I2C3
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UINT16 FPD3; ///< Offset 639 FPCN-HOLD for I2C3
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UINT16 HSH3; ///< Offset 641 HSCN-HIGH for I2C3
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UINT16 HSL3; ///< Offset 643 HSCN-LOW for I2C3
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UINT16 HSD3; ///< Offset 645 HSCN-HOLD for I2C3
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UINT8 Reserved5[1]; ///< Offset 647:647
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UINT16 SSH4; ///< Offset 648 SSCN-HIGH for I2C4
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UINT16 SSL4; ///< Offset 650 SSCN-LOW for I2C4
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UINT16 SSD4; ///< Offset 652 SSCN-HOLD for I2C4
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UINT16 FMH4; ///< Offset 654 FMCN-HIGH for I2C4
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UINT16 FML4; ///< Offset 656 FMCN-LOW for I2C4
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UINT16 FMD4; ///< Offset 658 FMCN-HOLD for I2C4
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UINT16 FPH4; ///< Offset 660 FPCN-HIGH for I2C4
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UINT16 FPL4; ///< Offset 662 FPCN-LOW for I2C4
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UINT16 FPD4; ///< Offset 664 FPCN-HOLD for I2C4
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UINT16 HSH4; ///< Offset 666 HSCN-HIGH for I2C4
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UINT16 HSL4; ///< Offset 668 HSCN-LOW for I2C4
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UINT16 HSD4; ///< Offset 670 HSCN-HOLD for I2C4
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UINT8 Reserved6[1]; ///< Offset 672:672
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UINT16 SSH5; ///< Offset 673 SSCN-HIGH for I2C5
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UINT16 SSL5; ///< Offset 675 SSCN-LOW for I2C5
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UINT16 SSD5; ///< Offset 677 SSCN-HOLD for I2C5
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UINT16 FMH5; ///< Offset 679 FMCN-HIGH for I2C5
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UINT16 FML5; ///< Offset 681 FMCN-LOW for I2C5
|
|
UINT16 FMD5; ///< Offset 683 FMCN-HOLD for I2C5
|
|
UINT16 FPH5; ///< Offset 685 FPCN-HIGH for I2C5
|
|
UINT16 FPL5; ///< Offset 687 FPCN-LOW for I2C5
|
|
UINT16 FPD5; ///< Offset 689 FPCN-HOLD for I2C5
|
|
UINT16 HSH5; ///< Offset 691 HSCN-HIGH for I2C5
|
|
UINT16 HSL5; ///< Offset 693 HSCN-LOW for I2C5
|
|
UINT16 HSD5; ///< Offset 695 HSCN-HOLD for I2C5
|
|
UINT8 Reserved7[1]; ///< Offset 697:697
|
|
UINT16 M0C0; ///< Offset 698 M0D3 for I2C0
|
|
UINT16 M1C0; ///< Offset 700 M1D3 for I2C0
|
|
UINT16 M0C1; ///< Offset 702 M0D3 for I2C1
|
|
UINT16 M1C1; ///< Offset 704 M1D3 for I2C1
|
|
UINT16 M0C2; ///< Offset 706 M0D3 for I2C2
|
|
UINT16 M1C2; ///< Offset 708 M1D3 for I2C2
|
|
UINT16 M0C3; ///< Offset 710 M0D3 for I2C3
|
|
UINT16 M1C3; ///< Offset 712 M1D3 for I2C3
|
|
UINT16 M0C4; ///< Offset 714 M0D3 for I2C4
|
|
UINT16 M1C4; ///< Offset 716 M1D3 for I2C4
|
|
UINT16 M0C5; ///< Offset 718 M0D3 for I2C5
|
|
UINT16 M1C5; ///< Offset 720 M1D3 for I2C5
|
|
UINT16 M0C6; ///< Offset 722 M0D3 for SPI0
|
|
UINT16 M1C6; ///< Offset 724 M1D3 for SPI0
|
|
UINT16 M0C7; ///< Offset 726 M0D3 for SPI1
|
|
UINT16 M1C7; ///< Offset 728 M1D3 for SPI1
|
|
UINT16 M0C8; ///< Offset 730 M0D3 for SPI2
|
|
UINT16 M1C8; ///< Offset 732 M1D3 for SPI2
|
|
UINT8 Reserved8[1]; ///< Offset 734:734
|
|
UINT16 M0C9; ///< Offset 735 M0D3 for UART0
|
|
UINT16 M1C9; ///< Offset 737 M1D3 for UART0
|
|
UINT16 M0CA; ///< Offset 739 M0D3 for UART1
|
|
UINT16 M1CA; ///< Offset 741 M1D3 for UART1
|
|
UINT16 M0CB; ///< Offset 743 M0D3 for UART2
|
|
UINT16 M1CB; ///< Offset 745 M1D3 for UART2
|
|
UINT8 Reserved9[1]; ///< Offset 747:747
|
|
//
|
|
// Driver Mode
|
|
//
|
|
UINT32 GpioIrqRoute; ///< Offset 748 GPIO IRQ
|
|
UINT8 DriverModeTouchPanel; ///< Offset 752 PIRQS 34,50(GPIO)
|
|
UINT8 DriverModeTouchPad; ///< Offset 753 PIRQX 39,55(GPIO)
|
|
UINT8 DriverModeSensorHub; ///< Offset 754 PIRQM 28,14(GPIO)
|
|
UINT8 SensorStandby; ///< Offset 755 Sensor Standby mode
|
|
UINT8 PL1LimitCS; ///< Offset 756 set PL1 limit when entering CS
|
|
UINT16 PL1LimitCSValue; ///< Offset 757 PL1 limit value
|
|
UINT8 EnableWwanTempSensorDevice; ///< Offset 759 EnableWwanTempSensorDevice
|
|
UINT8 EnableCpuVrTempSensorDevice; ///< Offset 760 EnableCpuVrTempSensorDevice
|
|
UINT8 EnableSsdTempSensorDevice; ///< Offset 761 EnableSsdTempSensorDevice
|
|
UINT8 EnableInletFanTempSensorDevice; ///< Offset 762 EnableInletFanTempSensorDevice
|
|
UINT8 ActiveThermalTripPointInletFan; ///< Offset 763 ActiveThermalTripPointInletFan
|
|
UINT8 PassiveThermalTripPointInletFan; ///< Offset 764 PassiveThermalTripPointInletFan
|
|
UINT8 CriticalThermalTripPointInletFan; ///< Offset 765 CriticalThermalTripPointInletFan
|
|
UINT8 HotThermalTripPointInletFan; ///< Offset 766 HotThermalTripPointInletFan
|
|
UINT8 UsbSensorHub; ///< Offset 767 Sensor Hub Type - (0)None, (1)USB, (2)I2C Intel, (3)I2C STM
|
|
UINT8 BCV4; ///< Offset 768 Broadcom's Bluetooth adapter's revision
|
|
UINT8 WTV0; ///< Offset 769 I2C0/WITT devices version
|
|
UINT8 WTV1; ///< Offset 770 I2C1/WITT devices version
|
|
UINT8 AtmelPanelFwUpdate; ///< Offset 771 Atmel panel FW update Enable/Disable
|
|
UINT8 Reserved10[6]; ///< Offset 772:777
|
|
UINT32 LowPowerS0IdleConstraint; ///< Offset 778 PEP Constraints
|
|
// Bit[1:0] - Storage (0:None, 1:Storage Controller, 2:Raid)
|
|
// Bit[2] - En/Dis UART0
|
|
// Bit[3] - En/Dis UART1
|
|
// Bit[4] - Unused
|
|
// Bit[5] - En/Dis I2C0
|
|
// Bit[6] - En/Dis I2C1
|
|
// Bit[7] - En/Dis XHCI
|
|
// Bit[8] - En/Dis HD Audio (includes ADSP)
|
|
// Bit[9] - En/Dis Gfx
|
|
// Bit[10] - En/Dis CPU
|
|
// Bit[11] - En/Dis EMMC
|
|
// Bit[12] - En/Dis SDXC
|
|
// Bit[13] - En/Dis I2C2
|
|
// Bit[14] - En/Dis I2C3
|
|
// Bit[15] - En/Dis I2C4
|
|
// Bit[16] - En/Dis I2C5
|
|
// Bit[17] - En/Dis UART2
|
|
// Bit[18] - En/Dis SPI0
|
|
// Bit[19] - En/Dis SPI1
|
|
// Bit[20] - [CNL] En/Dis SPI2
|
|
// Bit[21] - En/Dis IPU0
|
|
// Bit[22] - En/Dis CSME
|
|
// Bit[23] - En/Dis LAN(GBE)
|
|
UINT16 VRStaggeringDelay; ///< Offset 782 VR Staggering delay
|
|
UINT8 TenSecondPowerButtonEnable; ///< Offset 784 10sec Power button support
|
|
// Bit0: 10 sec P-button Enable/Disable
|
|
// Bit1: Internal Flag
|
|
// Bit2: Rotation Lock flag, 0:unlock, 1:lock
|
|
// Bit3: Slate/Laptop Mode Flag, 0: Slate, 1: Laptop
|
|
// Bit4: Undock / Dock Flag, 0: Undock, 1: Dock
|
|
// Bit5: VBDL Flag. 0: VBDL is not called, 1: VBDL is called, Virtual Button Driver is loaded.
|
|
// Bit6: Reserved for future use.
|
|
// Bit7: EC 10sec PB Override state for S3/S4 wake up.
|
|
//
|
|
// Generation Id(Tock/Tick)
|
|
//
|
|
UINT8 GenerationId; ///< Offset 785 Generation Id(0=Shark bay, 1=Crescent Bay)
|
|
//
|
|
// DPTF
|
|
//
|
|
UINT8 EnableWWANParticipant; ///< Offset 786 EnableWWANParticipant
|
|
UINT8 ActiveThermalTripPointWWAN; ///< Offset 787 ActiveThermalTripPointWWAN
|
|
UINT8 PassiveThermalTripPointWWAN; ///< Offset 788 PassiveThermalTripPointWWAN
|
|
UINT8 CriticalThermalTripPointWWAN; ///< Offset 789 CriticalThermalTripPointWWAN
|
|
UINT8 HotThermalTripPointWWAN; ///< Offset 790 HotThermalTripPointWWAN
|
|
UINT8 Reserved11[16]; ///< Offset 791:806
|
|
UINT16 MinPowerLimit0; ///< Offset 807 Minimum Power Limit 0 for DPTF use via PPCC Object
|
|
UINT8 EnableChargerParticipant; ///< Offset 809 EnableChargerParticipant
|
|
UINT8 CriticalThermalTripPointSaS3; ///< Offset 810 CriticalThermalTripPointSaS3
|
|
UINT8 CriticalThermalTripPointAmbientS3; ///< Offset 811 CriticalThermalTripPointAmbientS3
|
|
UINT8 CriticalThermalTripPointSkinS3; ///< Offset 812 CriticalThermalTripPointSkinS3
|
|
UINT8 CriticalThermalTripPointExhaustFanS3; ///< Offset 813 CriticalThermalTripPointExhaustFanS3
|
|
UINT8 CriticalThermalTripPointVrS3; ///< Offset 814 CriticalThermalTripPointVRS3
|
|
UINT8 CriticalThermalTripPointWrlsS3; ///< Offset 815 CriticalThermalTripPointWrlsS3
|
|
UINT8 CriticalThermalTripPointInletFanS3; ///< Offset 816 CriticalThermalTripPointInletFanS3
|
|
UINT8 CriticalThermalTripPointWwanS3; ///< Offset 817 CriticalThermalTripPointWWANS3
|
|
UINT8 CriticalThermalTripPointWGigS3; ///< Offset 818 CriticalThermalTripPointWGigS3
|
|
UINT8 SataPortState; ///< Offset 819 SATA port state, Bit0 - Port0, Bit1 - Port1, Bit2 - Port2, Bit3 - Port3
|
|
//
|
|
// DPTF
|
|
//
|
|
UINT8 Enable2DCameraParticipant; ///< Offset 820 Enable2DCameraParticipant
|
|
UINT8 EnableBatteryParticipant; ///< Offset 821 EnableBatteryParticipant
|
|
UINT8 EcLowPowerMode; ///< Offset 822 EC Low Power Mode: 1 - Enabled, 0 - Disabled
|
|
UINT8 SensorSamplingPeriodSen1; ///< Offset 823 SensorSamplingPeriodSen1
|
|
UINT8 SensorSamplingPeriodSen2; ///< Offset 824 SensorSamplingPeriodSen2
|
|
UINT8 SensorSamplingPeriodSen3; ///< Offset 825 SensorSamplingPeriodSen3
|
|
UINT8 SensorSamplingPeriodSen4; ///< Offset 826 SensorSamplingPeriodSen4
|
|
UINT8 SensorSamplingPeriodSen5; ///< Offset 827 SensorSamplingPeriodSen5
|
|
UINT8 ThermalSamplingPeriodTMEM; ///< Offset 828 ThermalSamplingPeriodTMEM @deprecated. Memory Participant is not POR for DPTF
|
|
UINT8 EnableStorageParticipantST1; ///< Offset 829 EnableStorageParticipantST1
|
|
UINT8 ActiveThermalTripPointST1; ///< Offset 830 ActiveThermalTripPointST1
|
|
UINT8 PassiveThermalTripPointST1; ///< Offset 831 PassiveThermalTripPointST1
|
|
UINT8 CriticalThermalTripPointST1; ///< Offset 832 CriticalThermalTripPointST1
|
|
UINT8 CriticalThermalTripPointS3ST1; ///< Offset 833 CriticalThermalTripPointS3ST1
|
|
UINT8 HotThermalTripPointST1; ///< Offset 834 HotThermalTripPointST1
|
|
UINT8 EnableStorageParticipantST2; ///< Offset 835 EnableStorageParticipantST2
|
|
UINT8 ActiveThermalTripPointST2; ///< Offset 836 ActiveThermalTripPointST2
|
|
UINT8 PassiveThermalTripPointST2; ///< Offset 837 PassiveThermalTripPointST2
|
|
UINT8 CriticalThermalTripPointST2; ///< Offset 838 CriticalThermalTripPointST2
|
|
UINT8 CriticalThermalTripPointS3ST2; ///< Offset 839 CriticalThermalTripPointS3ST2
|
|
UINT8 HotThermalTripPointST2; ///< Offset 840 HotThermalTripPointST2
|
|
UINT8 EnableVS1Participant; ///< Offset 841 EnableVS1Participant
|
|
UINT8 ActiveThermalTripPointVS1; ///< Offset 842 ActiveThermalTripPointVS1
|
|
UINT8 PassiveThermalTripPointVS1; ///< Offset 843 PassiveThermalTripPointVS1
|
|
UINT8 CriticalThermalTripPointVS1; ///< Offset 844 CriticalThermalTripPointVS1
|
|
UINT8 CriticalThermalTripPointVS1S3; ///< Offset 845 CriticalThermalTripPointVS1S3
|
|
UINT8 HotThermalTripPointVS1; ///< Offset 846 HotThermalTripPointVS1
|
|
UINT8 EnableVS2Participant; ///< Offset 847 EnableVS2Participant
|
|
UINT8 ActiveThermalTripPointVS2; ///< Offset 848 ActiveThermalTripPointVS2
|
|
UINT8 PassiveThermalTripPointVS2; ///< Offset 849 PassiveThermalTripPointVS2
|
|
UINT8 CriticalThermalTripPointVS2; ///< Offset 850 CriticalThermalTripPointVS2
|
|
UINT8 CriticalThermalTripPointVS2S3; ///< Offset 851 CriticalThermalTripPointVS2S3
|
|
UINT8 HotThermalTripPointVS2; ///< Offset 852 HotThermalTripPointVS2
|
|
UINT8 EnableSen1Participant; ///< Offset 853 EnableSen1Participant
|
|
UINT8 ActiveThermalTripPointSen1; ///< Offset 854 ActiveThermalTripPointSen1
|
|
UINT8 PassiveThermalTripPointSen1; ///< Offset 855 PassiveThermalTripPointSen1
|
|
UINT8 CriticalThermalTripPointSen1; ///< Offset 856 CriticalThermalTripPointSen1
|
|
UINT8 HotThermalTripPointSen1; ///< Offset 857 HotThermalTripPointSen1
|
|
UINT8 EnableSen2Participant; ///< Offset 858 EnableSen2Participant
|
|
UINT8 ActiveThermalTripPointSen2; ///< Offset 859 ActiveThermalTripPointSen2
|
|
UINT8 PassiveThermalTripPointSen2; ///< Offset 860 PassiveThermalTripPointSen2
|
|
UINT8 CriticalThermalTripPointSen2; ///< Offset 861 CriticalThermalTripPointSen2
|
|
UINT8 HotThermalTripPointSen2; ///< Offset 862 HotThermalTripPointSen2
|
|
UINT8 EnableSen3Participant; ///< Offset 863 EnableSen3Participant
|
|
UINT8 ActiveThermalTripPointSen3; ///< Offset 864 ActiveThermalTripPointSen3
|
|
UINT8 PassiveThermalTripPointSen3; ///< Offset 865 PassiveThermalTripPointSen3
|
|
UINT8 CriticalThermalTripPointSen3; ///< Offset 866 CriticalThermalTripPointSen3
|
|
UINT8 HotThermalTripPointSen3; ///< Offset 867 HotThermalTripPointSen3
|
|
UINT8 EnableSen4Participant; ///< Offset 868 EnableSen4Participant
|
|
UINT8 ActiveThermalTripPointSen4; ///< Offset 869 ActiveThermalTripPointSen4
|
|
UINT8 PassiveThermalTripPointSen4; ///< Offset 870 PassiveThermalTripPointSen4
|
|
UINT8 CriticalThermalTripPointSen4; ///< Offset 871 CriticalThermalTripPointSen4
|
|
UINT8 HotThermalTripPointSen4; ///< Offset 872 HotThermalTripPointSen4
|
|
UINT8 EnableSen5Participant; ///< Offset 873 EnableSen5Participant
|
|
UINT8 ActiveThermalTripPointSen5; ///< Offset 874 ActiveThermalTripPointSen5
|
|
UINT8 PassiveThermalTripPointSen5; ///< Offset 875 PassiveThermalTripPointSen5
|
|
UINT8 CriticalThermalTripPointSen5; ///< Offset 876 CriticalThermalTripPointSen5
|
|
UINT8 HotThermalTripPointSen5; ///< Offset 877 HotThermalTripPointSen5
|
|
UINT8 CriticalThermalTripPointSen1S3; ///< Offset 878 CriticalThermalTripPointSen1S3
|
|
UINT8 CriticalThermalTripPointSen2S3; ///< Offset 879 CriticalThermalTripPointSen2S3
|
|
UINT8 CriticalThermalTripPointSen3S3; ///< Offset 880 CriticalThermalTripPointSen3S3
|
|
UINT8 CriticalThermalTripPointSen4S3; ///< Offset 881 CriticalThermalTripPointSen4S3
|
|
UINT8 CriticalThermalTripPointSen5S3; ///< Offset 882 CriticalThermalTripPointSen5S3
|
|
UINT8 PowerSharingManagerEnable; ///< Offset 883 PowerSharingManagerEnable
|
|
UINT8 PsmSplcDomainType1; ///< Offset 884 PsmSplcDomainType1
|
|
UINT32 PsmSplcPowerLimit1; ///< Offset 885 PsmSplcPowerLimit1
|
|
UINT32 PsmSplcTimeWindow1; ///< Offset 889 PsmSplcTimeWindow1
|
|
UINT8 PsmSplcDomainType2; ///< Offset 893 PsmSplcDomainType2
|
|
UINT32 PsmSplcPowerLimit2; ///< Offset 894 PsmSplcPowerLimit2
|
|
UINT32 PsmSplcTimeWindow2; ///< Offset 898 PsmSplcTimeWindow2
|
|
UINT8 PsmDplcDomainType1; ///< Offset 902 PsmDplcDomainType1
|
|
UINT8 PsmDplcDomainPreference1; ///< Offset 903 PsmDplcDomainPreference1
|
|
UINT16 PsmDplcPowerLimitIndex1; ///< Offset 904 PsmDplcPowerLimitIndex1
|
|
UINT16 PsmDplcDefaultPowerLimit1; ///< Offset 906 PsmDplcDefaultPowerLimit1
|
|
UINT32 PsmDplcDefaultTimeWindow1; ///< Offset 908 PsmDplcDefaultTimeWindow1
|
|
UINT16 PsmDplcMinimumPowerLimit1; ///< Offset 912 PsmDplcMinimumPowerLimit1
|
|
UINT16 PsmDplcMaximumPowerLimit1; ///< Offset 914 PsmDplcMaximumPowerLimit1
|
|
UINT16 PsmDplcMaximumTimeWindow1; ///< Offset 916 PsmDplcMaximumTimeWindow1
|
|
UINT8 PsmDplcDomainType2; ///< Offset 918 PsmDplcDomainType2
|
|
UINT8 PsmDplcDomainPreference2; ///< Offset 919 PsmDplcDomainPreference2
|
|
UINT16 PsmDplcPowerLimitIndex2; ///< Offset 920 PsmDplcPowerLimitIndex2
|
|
UINT16 PsmDplcDefaultPowerLimit2; ///< Offset 922 PsmDplcDefaultPowerLimit2
|
|
UINT32 PsmDplcDefaultTimeWindow2; ///< Offset 924 PsmDplcDefaultTimeWindow2
|
|
UINT16 PsmDplcMinimumPowerLimit2; ///< Offset 928 PsmDplcMinimumPowerLimit2
|
|
UINT16 PsmDplcMaximumPowerLimit2; ///< Offset 930 PsmDplcMaximumPowerLimit2
|
|
UINT16 PsmDplcMaximumTimeWindow2; ///< Offset 932 PsmDplcMaximumTimeWindow2
|
|
UINT8 WifiEnable; ///< Offset 934 WifiEnable
|
|
UINT8 WifiDomainType1; ///< Offset 935 WifiDomainType1
|
|
UINT16 WifiPowerLimit1; ///< Offset 936 WifiPowerLimit1
|
|
UINT32 WifiTimeWindow1; ///< Offset 938 WifiTimeWindow1
|
|
UINT8 WifiDomainType2; ///< Offset 942 WifiDomainType2
|
|
UINT16 WifiPowerLimit2; ///< Offset 943 WifiPowerLimit2
|
|
UINT32 WifiTimeWindow2; ///< Offset 945 WifiTimeWindow2
|
|
UINT8 WifiDomainType3; ///< Offset 949 WifiDomainType3
|
|
UINT16 WifiPowerLimit3; ///< Offset 950 WifiPowerLimit3
|
|
UINT32 WifiTimeWindow3; ///< Offset 952 WifiTimeWindow3
|
|
UINT8 TRxDelay0; ///< Offset 956 TRxDelay0
|
|
UINT8 TRxCableLength0; ///< Offset 957 TRxCableLength0
|
|
UINT8 TRxDelay1; ///< Offset 958 TRxDelay1
|
|
UINT8 TRxCableLength1; ///< Offset 959 TRxCableLength1
|
|
UINT8 WrddDomainType1; ///< Offset 960 WrddDomainType1
|
|
UINT16 WrddCountryIndentifier1; ///< Offset 961 WrddCountryIndentifier1
|
|
UINT8 WrddDomainType2; ///< Offset 963 WrddDomainType2
|
|
UINT16 WrddCountryIndentifier2; ///< Offset 964 WrddCountryIndentifier2
|
|
UINT8 Reserved12[52]; ///< Offset 966:1017
|
|
UINT8 EnableAPPolicy; ///< Offset 1018 Adaptive Performance Policy
|
|
UINT16 MinPowerLimit1; ///< Offset 1019 Minimum Power Limit 1 for DPTF use via PPCC Object
|
|
UINT16 MinPowerLimit2; ///< Offset 1021 Minimum Power Limit 2 for DPTF use via PPCC Object
|
|
//
|
|
// Intel Serial(R) IO Sensor Device Selection
|
|
//
|
|
UINT8 SDS0; ///< Offset 1023 SerialIo Devices for controller0
|
|
UINT8 SDS1; ///< Offset 1024 SerialIo Devices for controller1
|
|
UINT8 SDS2; ///< Offset 1025 SerialIo Devices for controller2
|
|
UINT8 SDS3; ///< Offset 1026 SerialIo Devices for controller3
|
|
UINT8 SDS4; ///< Offset 1027 SerialIo Devices for controller4
|
|
UINT8 SDS5; ///< Offset 1028 SerialIo Devices for controller5
|
|
UINT8 SDS6; ///< Offset 1029 SerialIo Devices for controller6
|
|
UINT8 SDS7; ///< Offset 1030 SerialIo Devices for controller7
|
|
UINT8 SDS8; ///< Offset 1031 SerialIo Devices for controller8
|
|
UINT8 SDS9; ///< Offset 1032 SerialIo Devices for controller9
|
|
UINT8 SDSA; ///< Offset 1033 SerialIo Devices for controller10
|
|
UINT8 TPLT; ///< Offset 1034 I2C SerialIo Devices Type of TouchPanel
|
|
UINT8 TPLM; ///< Offset 1035 I2C SerialIo Devices Interrupt Mode for TouchPanel
|
|
UINT8 TPLB; ///< Offset 1036 I2C Custom TouchPanel's BUS Address
|
|
UINT16 TPLH; ///< Offset 1037 I2C Custom TouchPanel's HID Address
|
|
UINT8 TPLS; ///< Offset 1039 I2C Custom TouchPanel's BUS Speed
|
|
UINT8 TPDT; ///< Offset 1040 I2C SerialIo Devices Type of TouchPad
|
|
UINT8 TPDM; ///< Offset 1041 I2C SerialIo Devices Interrupt Mode for TouchPad
|
|
UINT8 TPDB; ///< Offset 1042 I2C Custom TouchPad's BUS Address
|
|
UINT16 TPDH; ///< Offset 1043 I2C Custom TouchPad's HID Address
|
|
UINT8 TPDS; ///< Offset 1045 I2C Custom TouchPad's BUS Speed
|
|
UINT8 FPTT; ///< Offset 1046 SPI SerialIo Devices Type of FingerPrint
|
|
UINT8 FPTM; ///< Offset 1047 SPI SerialIo Devices Interrupt Mode for FingerPrint
|
|
UINT8 WTVX; ///< Offset 1048 WITT test devices' version
|
|
UINT8 WITX; ///< Offset 1049 WITT test devices' connection point
|
|
UINT8 GPTD; ///< Offset 1050 GPIO test devices
|
|
UINT16 GDBT; ///< Offset 1051 GPIO test devices' debounce value,
|
|
UINT8 UTKX; ///< Offset 1053 UTK test devices' connection point
|
|
UINT8 SPTD; ///< Offset 1054 SerialIo additional test devices
|
|
UINT8 Reserved13[11]; ///< Offset 1055:1065
|
|
UINT32 TableLoadBuffer; ///< Offset 1066 Buffer for runtime ACPI Table loading
|
|
UINT8 SDM0; ///< Offset 1070 interrupt mode for controller0 devices
|
|
UINT8 SDM1; ///< Offset 1071 interrupt mode for controller1 devices
|
|
UINT8 SDM2; ///< Offset 1072 interrupt mode for controller2 devices
|
|
UINT8 SDM3; ///< Offset 1073 interrupt mode for controller3 devices
|
|
UINT8 SDM4; ///< Offset 1074 interrupt mode for controller4 devices
|
|
UINT8 SDM5; ///< Offset 1075 interrupt mode for controller5 devices
|
|
UINT8 SDM6; ///< Offset 1076 interrupt mode for controller6 devices
|
|
UINT8 SDM7; ///< Offset 1077 interrupt mode for controller7 devices
|
|
UINT8 SDM8; ///< Offset 1078 interrupt mode for controller8 devices
|
|
UINT8 SDM9; ///< Offset 1079 interrupt mode for controller9 devices
|
|
UINT8 SDMA; ///< Offset 1080 interrupt mode for controller10 devices
|
|
UINT8 SDMB; ///< Offset 1081 interrupt mode for controller11 devices
|
|
UINT8 Reserved14[1]; ///< Offset 1082:1082
|
|
UINT8 USTP; ///< Offset 1083 use SerialIo timing parameters
|
|
UINT8 Reserved15[41]; ///< Offset 1084:1124
|
|
UINT32 FingerPrintSleepGpio; ///< Offset 1125 Gpio for fingerprint sleep
|
|
UINT32 FingerPrintIrqGpio; ///< Offset 1129 Gpio for fingerprint irq
|
|
UINT8 DiscreteGnssModule; ///< Offset 1133 GNSS module and its interface, 0=disabled, 1=CG2000 over SerialIo Uart, 2=CG2000 over ISH Uart
|
|
UINT32 DiscreteGnssModuleResetGpio; ///< Offset 1134 Gpio for GNSS reset
|
|
UINT32 DiscreteBtModuleRfKillGpio; ///< Offset 1138 Gpio for Bluetooth RfKill
|
|
UINT32 DiscreteBtModuleIrqGpio; ///< Offset 1142 Gpio for Bluetooth interrupt
|
|
UINT32 TouchpadIrqGpio; ///< Offset 1146 Gpio for touchPaD Interrupt
|
|
UINT32 TouchpanelIrqGpio; ///< Offset 1150 Gpio for touchPaneL Interrupt
|
|
UINT8 DiscreteBtUartSupport; ///< Offset 1154 Switch to enable BT UART Support
|
|
UINT8 DiscreteGnssSupport; ///< Offset 1155 Switch to enable GNSS Support
|
|
//
|
|
// MipiCam specific
|
|
//
|
|
UINT8 MipiCamControlLogic0; ///< Offset 1156
|
|
UINT8 MipiCamControlLogic1; ///< Offset 1157
|
|
UINT8 MipiCamControlLogic2; ///< Offset 1158
|
|
UINT8 MipiCamControlLogic3; ///< Offset 1159
|
|
UINT8 MipiCamLink0Enabled; ///< Offset 1160
|
|
UINT8 MipiCamLink1Enabled; ///< Offset 1161
|
|
UINT8 MipiCamLink2Enabled; ///< Offset 1162
|
|
UINT8 MipiCamLink3Enabled; ///< Offset 1163
|
|
UINT8 MipiCamLanesClkDiv; ///< Offset 1164
|
|
// Control Logic 0 options
|
|
UINT8 MipiCamCtrlLogic0_Version; ///< Offset 1165 Version of CLDB structure
|
|
UINT8 MipiCamCtrlLogic0_Type; ///< Offset 1166 Type
|
|
UINT8 MipiCamCtrlLogic0_CrdVersion; ///< Offset 1167 Version of CRD
|
|
UINT32 MipiCamCtrlLogic0_InputClock; ///< Offset 1168 Input Clock
|
|
UINT8 MipiCamCtrlLogic0_GpioPinsEnabled; ///< Offset 1172 Number of GPIO Pins enabled
|
|
UINT8 MipiCamCtrlLogic0_I2cBus; ///< Offset 1173 I2C Serial Bus Number
|
|
UINT16 MipiCamCtrlLogic0_I2cAddress; ///< Offset 1174 I2C Address
|
|
UINT8 MipiCamCtrlLogic0_GpioGroupPadNumber[4]; ///< Offset 1176 GPIO Group Pad Number
|
|
UINT8 MipiCamCtrlLogic0_GpioGroupNumber[4]; ///< Offset 1180 GPIO Group Number
|
|
UINT8 MipiCamCtrlLogic0_GpioFunction[4]; ///< Offset 1184 GPIO Function
|
|
UINT8 MipiCamCtrlLogic0_GpioActiveValue[4]; ///< Offset 1188 GPIO Active Value
|
|
UINT8 MipiCamCtrlLogic0_GpioInitialValue[4]; ///< Offset 1192 GPIO Initial Value
|
|
UINT8 MipiCamCtrlLogic0_Pld; ///< Offset 1196 Camera Position
|
|
UINT8 MipiCamCtrlLogic0_Wled1FlashMaxCurrent; ///< Offset 1197 WLED1 Flash Max Current
|
|
UINT8 MipiCamCtrlLogic0_Wled1TorchMaxCurrent; ///< Offset 1198 WLED1 Torch Max Current
|
|
UINT8 MipiCamCtrlLogic0_Wled2FlashMaxCurrent; ///< Offset 1199 WLED2 Flash Max Current
|
|
UINT8 MipiCamCtrlLogic0_Wled2TorchMaxCurrent; ///< Offset 1200 WLED2 Torch Max Current
|
|
UINT8 MipiCamCtrlLogic0_SubPlatformId; ///< Offset 1201 Sub Platform Id
|
|
UINT8 MipiCamCtrlLogic0_Wled1Type; ///< Offset 1202 WLED1 Type
|
|
UINT8 MipiCamCtrlLogic0_Wled2Type; ///< Offset 1203 WLED2 Type
|
|
UINT8 MipiCamCtrlLogic0_PchClockSource; ///< Offset 1204 PCH Clock source
|
|
// Control Logic 1 options
|
|
UINT8 MipiCamCtrlLogic1_Version; ///< Offset 1205 Version of CLDB structure
|
|
UINT8 MipiCamCtrlLogic1_Type; ///< Offset 1206 Type
|
|
UINT8 MipiCamCtrlLogic1_CrdVersion; ///< Offset 1207 Version of CRD
|
|
UINT32 MipiCamCtrlLogic1_InputClock; ///< Offset 1208 Input Clock
|
|
UINT8 MipiCamCtrlLogic1_GpioPinsEnabled; ///< Offset 1212 Number of GPIO Pins enabled
|
|
UINT8 MipiCamCtrlLogic1_I2cBus; ///< Offset 1213 I2C Serial Bus Number
|
|
UINT16 MipiCamCtrlLogic1_I2cAddress; ///< Offset 1214 I2C Address
|
|
UINT8 MipiCamCtrlLogic1_GpioGroupPadNumber[4]; ///< Offset 1216 GPIO Group Pad Number
|
|
UINT8 MipiCamCtrlLogic1_GpioGroupNumber[4]; ///< Offset 1220 GPIO Group Number
|
|
UINT8 MipiCamCtrlLogic1_GpioFunction[4]; ///< Offset 1224 GPIO Function
|
|
UINT8 MipiCamCtrlLogic1_GpioActiveValue[4]; ///< Offset 1228 GPIO Active Value
|
|
UINT8 MipiCamCtrlLogic1_GpioInitialValue[4]; ///< Offset 1232 GPIO Initial Value
|
|
UINT8 MipiCamCtrlLogic1_Pld; ///< Offset 1236 Camera Position
|
|
UINT8 MipiCamCtrlLogic1_Wled1FlashMaxCurrent; ///< Offset 1237 WLED1 Flash Max Current
|
|
UINT8 MipiCamCtrlLogic1_Wled1TorchMaxCurrent; ///< Offset 1238 WLED1 Torch Max Current
|
|
UINT8 MipiCamCtrlLogic1_Wled2FlashMaxCurrent; ///< Offset 1239 WLED2 Flash Max Current
|
|
UINT8 MipiCamCtrlLogic1_Wled2TorchMaxCurrent; ///< Offset 1240 WLED2 Torch Max Current
|
|
UINT8 MipiCamCtrlLogic1_SubPlatformId; ///< Offset 1241 Sub Platform Id
|
|
UINT8 MipiCamCtrlLogic1_Wled1Type; ///< Offset 1242 WLED1 Type
|
|
UINT8 MipiCamCtrlLogic1_Wled2Type; ///< Offset 1243 WLED2 Type
|
|
UINT8 MipiCamCtrlLogic1_PchClockSource; ///< Offset 1244 PCH Clock source
|
|
// Control Logic 2 options
|
|
UINT8 MipiCamCtrlLogic2_Version; ///< Offset 1245 Version of CLDB structure
|
|
UINT8 MipiCamCtrlLogic2_Type; ///< Offset 1246 Type
|
|
UINT8 MipiCamCtrlLogic2_CrdVersion; ///< Offset 1247 Version of CRD
|
|
UINT32 MipiCamCtrlLogic2_InputClock; ///< Offset 1248 Input Clock
|
|
UINT8 MipiCamCtrlLogic2_GpioPinsEnabled; ///< Offset 1252 Number of GPIO Pins enabled
|
|
UINT8 MipiCamCtrlLogic2_I2cBus; ///< Offset 1253 I2C Serial Bus Number
|
|
UINT16 MipiCamCtrlLogic2_I2cAddress; ///< Offset 1254 I2C Address
|
|
UINT8 MipiCamCtrlLogic2_GpioGroupPadNumber[4]; ///< Offset 1256 GPIO Group Pad Number
|
|
UINT8 MipiCamCtrlLogic2_GpioGroupNumber[4]; ///< Offset 1260 GPIO Group Number
|
|
UINT8 MipiCamCtrlLogic2_GpioFunction[4]; ///< Offset 1264 GPIO Function
|
|
UINT8 MipiCamCtrlLogic2_GpioActiveValue[4]; ///< Offset 1268 GPIO Active Value
|
|
UINT8 MipiCamCtrlLogic2_GpioInitialValue[4]; ///< Offset 1272 GPIO Initial Value
|
|
UINT8 MipiCamCtrlLogic2_Pld; ///< Offset 1276 Camera Position
|
|
UINT8 MipiCamCtrlLogic2_Wled1FlashMaxCurrent; ///< Offset 1277 WLED1 Flash Max Current
|
|
UINT8 MipiCamCtrlLogic2_Wled1TorchMaxCurrent; ///< Offset 1278 WLED1 Torch Max Current
|
|
UINT8 MipiCamCtrlLogic2_Wled2FlashMaxCurrent; ///< Offset 1279 WLED2 Flash Max Current
|
|
UINT8 MipiCamCtrlLogic2_Wled2TorchMaxCurrent; ///< Offset 1280 WLED2 Torch Max Current
|
|
UINT8 MipiCamCtrlLogic2_SubPlatformId; ///< Offset 1281 Sub Platform Id
|
|
UINT8 MipiCamCtrlLogic2_Wled1Type; ///< Offset 1282 WLED1 Type
|
|
UINT8 MipiCamCtrlLogic2_Wled2Type; ///< Offset 1283 WLED2 Type
|
|
UINT8 MipiCamCtrlLogic2_PchClockSource; ///< Offset 1284 PCH Clock source
|
|
// Control Logic 3 options
|
|
UINT8 MipiCamCtrlLogic3_Version; ///< Offset 1285 Version of CLDB structure
|
|
UINT8 MipiCamCtrlLogic3_Type; ///< Offset 1286 Type
|
|
UINT8 MipiCamCtrlLogic3_CrdVersion; ///< Offset 1287 Version of CRD
|
|
UINT32 MipiCamCtrlLogic3_InputClock; ///< Offset 1288 Input Clock
|
|
UINT8 MipiCamCtrlLogic3_GpioPinsEnabled; ///< Offset 1292 Number of GPIO Pins enabled
|
|
UINT8 MipiCamCtrlLogic3_I2cBus; ///< Offset 1293 I2C Serial Bus Number
|
|
UINT16 MipiCamCtrlLogic3_I2cAddress; ///< Offset 1294 I2C Address
|
|
UINT8 MipiCamCtrlLogic3_GpioGroupPadNumber[4]; ///< Offset 1296 GPIO Group Pad Number
|
|
UINT8 MipiCamCtrlLogic3_GpioGroupNumber[4]; ///< Offset 1300 GPIO Group Number
|
|
UINT8 MipiCamCtrlLogic3_GpioFunction[4]; ///< Offset 1304 GPIO Function
|
|
UINT8 MipiCamCtrlLogic3_GpioActiveValue[4]; ///< Offset 1308 GPIO Active Value
|
|
UINT8 MipiCamCtrlLogic3_GpioInitialValue[4]; ///< Offset 1312 GPIO Initial Value
|
|
UINT8 MipiCamCtrlLogic3_Pld; ///< Offset 1316 Camera Position
|
|
UINT8 MipiCamCtrlLogic3_Wled1FlashMaxCurrent; ///< Offset 1317 WLED1 Flash Max Current
|
|
UINT8 MipiCamCtrlLogic3_Wled1TorchMaxCurrent; ///< Offset 1318 WLED1 Torch Max Current
|
|
UINT8 MipiCamCtrlLogic3_Wled2FlashMaxCurrent; ///< Offset 1319 WLED2 Flash Max Current
|
|
UINT8 MipiCamCtrlLogic3_Wled2TorchMaxCurrent; ///< Offset 1320 WLED2 Torch Max Current
|
|
UINT8 MipiCamCtrlLogic3_SubPlatformId; ///< Offset 1321 Sub Platform Id
|
|
UINT8 MipiCamCtrlLogic3_Wled1Type; ///< Offset 1322 WLED1 Type
|
|
UINT8 MipiCamCtrlLogic3_Wled2Type; ///< Offset 1323 WLED2 Type
|
|
UINT8 MipiCamCtrlLogic3_PchClockSource; ///< Offset 1324 PCH Clock source
|
|
// Mipi Cam Link0 options
|
|
UINT8 MipiCamLink0SensorModel; ///< Offset 1325 Sensor Model
|
|
UINT8 MipiCamLink0UserHid[9]; ///< Offset 1326 User defined HID ASCII character 0
|
|
///< Offset 1334 User defined HID ASCII character 8
|
|
UINT8 MipiCamLink0Pld; ///< Offset 1335 Camera Position
|
|
UINT8 MipiCamLink0ModuleName[16]; ///< Offset 1336 Camera Module Name ASCII character 0
|
|
///< Offset 1351 Camera Module Name ASCII character 15
|
|
UINT8 MipiCamLink0I2cDevicesEnabled; ///< Offset 1352 Number of I2C devices
|
|
UINT8 MipiCamLink0I2cBus; ///< Offset 1353 I2C Serial Bus number
|
|
UINT16 MipiCamLink0I2cAddrDev[12]; ///< Offset 1354 Address of I2C Device0 on Link0
|
|
///< Offset 1356 Address of I2C Device1 on Link0
|
|
///< Offset 1358 Address of I2C Device2 on Link0
|
|
///< Offset 1360 Address of I2C Device3 on Link0
|
|
///< Offset 1362 Address of I2C Device4 on Link0
|
|
///< Offset 1364 Address of I2C Device5 on Link0
|
|
///< Offset 1366 Address of I2C Device6 on Link0
|
|
///< Offset 1368 Address of I2C Device7 on Link0
|
|
///< Offset 1370 Address of I2C Device8 on Link0
|
|
///< Offset 1372 Address of I2C Device9 on Link0
|
|
///< Offset 1374 Address of I2C Device10 on Link0
|
|
///< Offset 1376 Address of I2C Device11 on Link0
|
|
UINT8 MipiCamLink0I2cDeviceType[12]; ///< Offset 1378 Type of I2C Device0 on Link0
|
|
///< Offset 1379 Type of I2C Device1 on Link0
|
|
///< Offset 1380 Type of I2C Device2 on Link0
|
|
///< Offset 1381 Type of I2C Device3 on Link0
|
|
///< Offset 1382 Type of I2C Device4 on Link0
|
|
///< Offset 1383 Type of I2C Device5 on Link0
|
|
///< Offset 1384 Type of I2C Device6 on Link0
|
|
///< Offset 1385 Type of I2C Device7 on Link0
|
|
///< Offset 1386 Type of I2C Device8 on Link0
|
|
///< Offset 1387 Type of I2C Device9 on Link0
|
|
///< Offset 1388 Type of I2C Device10 on Link0
|
|
///< Offset 1389 Type of I2C Device11 on Link0
|
|
UINT8 MipiCamLink0DD_Version; ///< Offset 1390 Version of SSDB structure
|
|
UINT8 MipiCamLink0DD_CrdVersion; ///< Offset 1391 Version of CRD
|
|
UINT8 MipiCamLink0DD_LinkUsed; ///< Offset 1392 CSI2 Link used
|
|
UINT8 MipiCamLink0DD_LaneUsed; ///< Offset 1393 MIPI-CSI2 Data Lane
|
|
UINT8 MipiCamLink0DD_EepromType; ///< Offset 1394 EEPROM Type
|
|
UINT8 MipiCamLink0DD_VcmType; ///< Offset 1395 VCM Type
|
|
UINT8 MipiCamLink0DD_FlashSupport; ///< Offset 1396 Flash Support
|
|
UINT8 MipiCamLink0DD_PrivacyLed; ///< Offset 1397 Privacy LED
|
|
UINT8 MipiCamLink0DD_Degree; ///< Offset 1398 Degree
|
|
UINT32 MipiCamLink0DD_Mclk; ///< Offset 1399 MCLK
|
|
UINT8 MipiCamLink0DD_ControlLogic; ///< Offset 1403 Control Logic
|
|
UINT8 MipiCamLink0DD_PmicPosition; ///< Offset 1404 PMIC Position
|
|
UINT8 MipiCamLink0DD_VoltageRail; ///< Offset 1405 Voltage Rail
|
|
// Mipi Cam Link1 options
|
|
UINT8 MipiCamLink1SensorModel; ///< Offset 1406 Sensor Model
|
|
UINT8 MipiCamLink1UserHid[9]; ///< Offset 1407 User defined HID ASCII character 0
|
|
///< Offset 1415 User defined HID ASCII character 8
|
|
UINT8 MipiCamLink1Pld; ///< Offset 1416 Camera Position
|
|
UINT8 MipiCamLink1ModuleName[16]; ///< Offset 1417 Camera Module Name ASCII character 0
|
|
///< Offset 1432 Camera Module Name ASCII character 15
|
|
UINT8 MipiCamLink1I2cDevicesEnabled; ///< Offset 1433 Number of I2C devices
|
|
UINT8 MipiCamLink1I2cBus; ///< Offset 1434 I2C Serial Bus number
|
|
UINT16 MipiCamLink1I2cAddrDev[12]; ///< Offset 1435 Address of I2C Device0 on Link1
|
|
///< Offset 1437 Address of I2C Device1 on Link1
|
|
///< Offset 1439 Address of I2C Device2 on Link1
|
|
///< Offset 1441 Address of I2C Device3 on Link1
|
|
///< Offset 1443 Address of I2C Device4 on Link1
|
|
///< Offset 1445 Address of I2C Device5 on Link1
|
|
///< Offset 1447 Address of I2C Device6 on Link1
|
|
///< Offset 1449 Address of I2C Device7 on Link1
|
|
///< Offset 1451 Address of I2C Device8 on Link1
|
|
///< Offset 1453 Address of I2C Device9 on Link1
|
|
///< Offset 1455 Address of I2C Device10 on Link1
|
|
///< Offset 1457 Address of I2C Device11 on Link1
|
|
UINT8 MipiCamLink1I2cDeviceType[12]; ///< Offset 1459 Type of I2C Device0 on Link1
|
|
///< Offset 1460 Type of I2C Device1 on Link1
|
|
///< Offset 1461 Type of I2C Device2 on Link1
|
|
///< Offset 1462 Type of I2C Device3 on Link1
|
|
///< Offset 1463 Type of I2C Device4 on Link1
|
|
///< Offset 1464 Type of I2C Device5 on Link1
|
|
///< Offset 1465 Type of I2C Device6 on Link1
|
|
///< Offset 1466 Type of I2C Device7 on Link1
|
|
///< Offset 1467 Type of I2C Device8 on Link1
|
|
///< Offset 1468 Type of I2C Device9 on Link1
|
|
///< Offset 1469 Type of I2C Device10 on Link1
|
|
///< Offset 1470 Type of I2C Device11 on Link1
|
|
UINT8 MipiCamLink1DD_Version; ///< Offset 1471 Version of SSDB structure
|
|
UINT8 MipiCamLink1DD_CrdVersion; ///< Offset 1472 Version of CRD
|
|
UINT8 MipiCamLink1DD_LinkUsed; ///< Offset 1473 CSI2 Link used
|
|
UINT8 MipiCamLink1DD_LaneUsed; ///< Offset 1474 MIPI-CSI2 Data Lane
|
|
UINT8 MipiCamLink1DD_EepromType; ///< Offset 1475 EEPROM Type
|
|
UINT8 MipiCamLink1DD_VcmType; ///< Offset 1476 VCM Type
|
|
UINT8 MipiCamLink1DD_FlashSupport; ///< Offset 1477 Flash Support
|
|
UINT8 MipiCamLink1DD_PrivacyLed; ///< Offset 1478 Privacy LED
|
|
UINT8 MipiCamLink1DD_Degree; ///< Offset 1479 Degree
|
|
UINT32 MipiCamLink1DD_Mclk; ///< Offset 1480 MCLK
|
|
UINT8 MipiCamLink1DD_ControlLogic; ///< Offset 1484 Control Logic
|
|
UINT8 MipiCamLink1DD_PmicPosition; ///< Offset 1485 PMIC Position
|
|
UINT8 MipiCamLink1DD_VoltageRail; ///< Offset 1486 Voltage Rail
|
|
// Mipi Cam Link2 options
|
|
UINT8 MipiCamLink2SensorModel; ///< Offset 1487 Sensor Model
|
|
UINT8 MipiCamLink2UserHid[9]; ///< Offset 1488 User defined HID ASCII character 0
|
|
///< Offset 1496 User defined HID ASCII character 8
|
|
UINT8 MipiCamLink2Pld; ///< Offset 1497 Camera Position
|
|
UINT8 MipiCamLink2ModuleName[16]; ///< Offset 1498 Camera Module Name ASCII character 0
|
|
///< Offset 1513 Camera Module Name ASCII character 15
|
|
UINT8 MipiCamLink2I2cDevicesEnabled; ///< Offset 1514 Number of I2C devices
|
|
UINT8 MipiCamLink2I2cBus; ///< Offset 1515 I2C Serial Bus number
|
|
UINT16 MipiCamLink2I2cAddrDev[12]; ///< Offset 1516 Address of I2C Device0 on Link2
|
|
///< Offset 1518 Address of I2C Device1 on Link2
|
|
///< Offset 1520 Address of I2C Device2 on Link2
|
|
///< Offset 1522 Address of I2C Device3 on Link2
|
|
///< Offset 1524 Address of I2C Device4 on Link2
|
|
///< Offset 1526 Address of I2C Device5 on Link2
|
|
///< Offset 1528 Address of I2C Device6 on Link2
|
|
///< Offset 1530 Address of I2C Device7 on Link2
|
|
///< Offset 1532 Address of I2C Device8 on Link2
|
|
///< Offset 1534 Address of I2C Device9 on Link2
|
|
///< Offset 1536 Address of I2C Device10 on Link2
|
|
///< Offset 1538 Address of I2C Device11 on Link2
|
|
UINT8 MipiCamLink2I2cDeviceType[12]; ///< Offset 1540 Type of I2C Device0 on Link2
|
|
///< Offset 1541 Type of I2C Device1 on Link2
|
|
///< Offset 1542 Type of I2C Device2 on Link2
|
|
///< Offset 1543 Type of I2C Device3 on Link2
|
|
///< Offset 1544 Type of I2C Device4 on Link2
|
|
///< Offset 1545 Type of I2C Device5 on Link2
|
|
///< Offset 1546 Type of I2C Device6 on Link2
|
|
///< Offset 1547 Type of I2C Device7 on Link2
|
|
///< Offset 1548 Type of I2C Device8 on Link2
|
|
///< Offset 1549 Type of I2C Device9 on Link2
|
|
///< Offset 1550 Type of I2C Device10 on Link2
|
|
///< Offset 1551 Type of I2C Device11 on Link2
|
|
UINT8 MipiCamLink2DD_Version; ///< Offset 1552 Version of SSDB structure
|
|
UINT8 MipiCamLink2DD_CrdVersion; ///< Offset 1553 Version of CRD
|
|
UINT8 MipiCamLink2DD_LinkUsed; ///< Offset 1554 CSI2 Link used
|
|
UINT8 MipiCamLink2DD_LaneUsed; ///< Offset 1555 MIPI-CSI2 Data Lane
|
|
UINT8 MipiCamLink2DD_EepromType; ///< Offset 1556 EEPROM Type
|
|
UINT8 MipiCamLink2DD_VcmType; ///< Offset 1557 VCM Type
|
|
UINT8 MipiCamLink2DD_FlashSupport; ///< Offset 1558 Flash Support
|
|
UINT8 MipiCamLink2DD_PrivacyLed; ///< Offset 1559 Privacy LED
|
|
UINT8 MipiCamLink2DD_Degree; ///< Offset 1560 Degree
|
|
UINT32 MipiCamLink2DD_Mclk; ///< Offset 1561 MCLK
|
|
UINT8 MipiCamLink2DD_ControlLogic; ///< Offset 1565 Control Logic
|
|
UINT8 MipiCamLink2DD_PmicPosition; ///< Offset 1566 PMIC Position
|
|
UINT8 MipiCamLink2DD_VoltageRail; ///< Offset 1567 Voltage Rail
|
|
// Mipi Cam Link3 options
|
|
UINT8 MipiCamLink3SensorModel; ///< Offset 1568 Sensor Model
|
|
UINT8 MipiCamLink3UserHid[9]; ///< Offset 1569 User defined HID ASCII character 0
|
|
///< Offset 1577 User defined HID ASCII character 8
|
|
UINT8 MipiCamLink3Pld; ///< Offset 1578 Camera Position
|
|
UINT8 MipiCamLink3ModuleName[16]; ///< Offset 1579 Camera Module Name ASCII character 0
|
|
///< Offset 1594 Camera Module Name ASCII character 15
|
|
UINT8 MipiCamLink3I2cDevicesEnabled; ///< Offset 1595 Number of I2C devices
|
|
UINT8 MipiCamLink3I2cBus; ///< Offset 1596 I2C Serial Bus number
|
|
UINT16 MipiCamLink3I2cAddrDev[12]; ///< Offset 1597 Address of I2C Device0 on Link3
|
|
///< Offset 1599 Address of I2C Device1 on Link3
|
|
///< Offset 1601 Address of I2C Device2 on Link3
|
|
///< Offset 1603 Address of I2C Device3 on Link3
|
|
///< Offset 1605 Address of I2C Device4 on Link3
|
|
///< Offset 1607 Address of I2C Device5 on Link3
|
|
///< Offset 1609 Address of I2C Device6 on Link3
|
|
///< Offset 1611 Address of I2C Device7 on Link3
|
|
///< Offset 1613 Address of I2C Device8 on Link3
|
|
///< Offset 1615 Address of I2C Device9 on Link3
|
|
///< Offset 1617 Address of I2C Device10 on Link3
|
|
///< Offset 1619 Address of I2C Device11 on Link3
|
|
UINT8 MipiCamLink3I2cDeviceType[12]; ///< Offset 1621 Type of I2C Device0 on Link3
|
|
///< Offset 1622 Type of I2C Device1 on Link3
|
|
///< Offset 1623 Type of I2C Device2 on Link3
|
|
///< Offset 1624 Type of I2C Device3 on Link3
|
|
///< Offset 1625 Type of I2C Device4 on Link3
|
|
///< Offset 1626 Type of I2C Device5 on Link3
|
|
///< Offset 1627 Type of I2C Device6 on Link3
|
|
///< Offset 1628 Type of I2C Device7 on Link3
|
|
///< Offset 1629 Type of I2C Device8 on Link3
|
|
///< Offset 1630 Type of I2C Device9 on Link3
|
|
///< Offset 1631 Type of I2C Device10 on Link3
|
|
///< Offset 1632 Type of I2C Device11 on Link3
|
|
UINT8 MipiCamLink3DD_Version; ///< Offset 1633 Version of SSDB structure
|
|
UINT8 MipiCamLink3DD_CrdVersion; ///< Offset 1634 Version of CRD
|
|
UINT8 MipiCamLink3DD_LinkUsed; ///< Offset 1635 CSI2 Link used
|
|
UINT8 MipiCamLink3DD_LaneUsed; ///< Offset 1636 MIPI-CSI2 Data Lane
|
|
UINT8 MipiCamLink3DD_EepromType; ///< Offset 1637 EEPROM Type
|
|
UINT8 MipiCamLink3DD_VcmType; ///< Offset 1638 VCM Type
|
|
UINT8 MipiCamLink3DD_FlashSupport; ///< Offset 1639 Flash Support
|
|
UINT8 MipiCamLink3DD_PrivacyLed; ///< Offset 1640 Privacy LED
|
|
UINT8 MipiCamLink3DD_Degree; ///< Offset 1641 Degree
|
|
UINT32 MipiCamLink3DD_Mclk; ///< Offset 1642 MCLK
|
|
UINT8 MipiCamLink3DD_ControlLogic; ///< Offset 1646 Control Logic
|
|
UINT8 MipiCamLink3DD_PmicPosition; ///< Offset 1647 PMIC Position
|
|
UINT8 MipiCamLink3DD_VoltageRail; ///< Offset 1648 Voltage Rail
|
|
UINT8 Reserved16[1]; ///< Offset 1649:1649
|
|
UINT8 PciDelayOptimizationEcr; ///< Offset 1650
|
|
UINT8 I2SC; ///< Offset 1651 HD Audio I2S Codec Selection
|
|
UINT32 I2SI; ///< Offset 1652 HD Audio I2S Codec Interrupt Pin
|
|
UINT8 I2SB; ///< Offset 1656 HD Audio I2S Codec Connection to I2C bus controller instance (I2C[0-5])
|
|
UINT8 OemDesignVariable0; ///< Offset 1657 DPTF Oem Design Variables
|
|
UINT8 OemDesignVariable1; ///< Offset 1658 DPTF Oem Design Variables
|
|
UINT8 OemDesignVariable2; ///< Offset 1659 DPTF Oem Design Variables
|
|
UINT8 OemDesignVariable3; ///< Offset 1660 DPTF Oem Design Variables
|
|
UINT8 OemDesignVariable4; ///< Offset 1661 DPTF Oem Design Variables
|
|
UINT8 OemDesignVariable5; ///< Offset 1662 DPTF Oem Design Variables
|
|
UINT32 UsbTypeCOpBaseAddr; ///< Offset 1663 USB Type C Opregion base address
|
|
UINT8 Reserved17[5]; ///< Offset 1667:1671
|
|
UINT8 WirelessCharging; ///< Offset 1672 WirelessCharging
|
|
// RTD3 Settings
|
|
UINT8 Reserved18[7]; ///< Offset 1673:1679
|
|
UINT32 HdaDspPpModuleMask; ///< Offset 1680 HD-Audio DSP Post-Processing Module Mask
|
|
UINT64 HdaDspPpModCustomGuid1Low; ///< Offset 1684 HDA PP module custom GUID 1 - first 64bit [0-63]
|
|
UINT64 HdaDspPpModCustomGuid1High; ///< Offset 1692 HDA PP module custom GUID 1 - second 64bit [64-127]
|
|
UINT64 HdaDspPpModCustomGuid2Low; ///< Offset 1700 HDA PP module custom GUID 2 - first 64bit [0-63]
|
|
UINT64 HdaDspPpModCustomGuid2High; ///< Offset 1708 HDA PP module custom GUID 2 - second 64bit [64-127]
|
|
UINT64 HdaDspPpModCustomGuid3Low; ///< Offset 1716 HDA PP module custom GUID 3 - first 64bit [0-63]
|
|
UINT64 HdaDspPpModCustomGuid3High; ///< Offset 1724 HDA PP module custom GUID 3 - second 64bit [64-127]
|
|
UINT8 HidEventFilterEnable; ///< Offset 1732 HID Event Filter Driver enable
|
|
UINT8 XdciFnEnable; ///< Offset 1733 XDCI Enable/Disable status
|
|
UINT8 WrdsWiFiSarEnable; ///< Offset 1734 WrdsWiFiSarEnable
|
|
UINT8 WrdsWiFiSarTxPowerSet1Limit1; ///< Offset 1735 WrdsWiFiSarTxPowerSet1Limit1
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UINT8 WrdsWiFiSarTxPowerSet1Limit2; ///< Offset 1736 WrdsWiFiSarTxPowerSet1Limit2
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UINT8 WrdsWiFiSarTxPowerSet1Limit3; ///< Offset 1737 WrdsWiFiSarTxPowerSet1Limit3
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UINT8 WrdsWiFiSarTxPowerSet1Limit4; ///< Offset 1738 WrdsWiFiSarTxPowerSet1Limit4
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UINT8 WrdsWiFiSarTxPowerSet1Limit5; ///< Offset 1739 WrdsWiFiSarTxPowerSet1Limit5
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UINT8 WrdsWiFiSarTxPowerSet1Limit6; ///< Offset 1740 WrdsWiFiSarTxPowerSet1Limit6
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UINT8 WrdsWiFiSarTxPowerSet1Limit7; ///< Offset 1741 WrdsWiFiSarTxPowerSet1Limit7
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UINT8 WrdsWiFiSarTxPowerSet1Limit8; ///< Offset 1742 WrdsWiFiSarTxPowerSet1Limit8
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UINT8 WrdsWiFiSarTxPowerSet1Limit9; ///< Offset 1743 WrdsWiFiSarTxPowerSet1Limit9
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|
UINT8 WrdsWiFiSarTxPowerSet1Limit10; ///< Offset 1744 WrdsWiFiSarTxPowerSet1Limit10
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|
UINT8 EnableVoltageMargining; ///< Offset 1745 Enable Voltage Margining
|
|
UINT16 DStateHSPort; ///< Offset 1746 D-State for xHCI HS port(BIT0:USB HS Port0 ~ BIT15:USB HS Port15)
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|
UINT16 DStateSSPort; ///< Offset 1748 D-State for xHCI SS port(BIT0:USB SS Port0 ~ BIT15:USB SS Port15)
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|
UINT8 DStateSataPort; ///< Offset 1750 D-State for SATA port(BIT0:SATA Port0 ~ BIT7:SATA Port7)
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|
UINT8 WigigRfe; ///< Offset 1751 WigigRfe
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|
UINT8 WiGigRfeCh1; ///< Offset 1752 WiGigRfeCh1
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UINT8 WiGigRfeCh2; ///< Offset 1753 WiGigRfeCh2
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UINT8 WiGigRfeCh3; ///< Offset 1754 WiGigRfeCh3
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|
UINT8 WiGigRfeCh4; ///< Offset 1755 WiGigRfeCh4
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|
UINT32 AwvClassIndex; ///< Offset 1756 AwvClassIndex
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|
UINT8 EwrdWiFiDynamicSarEnable; ///< Offset 1760 EwrdWiFiDynamicSarEnable
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|
UINT8 EwrdWiFiDynamicSarRangeSets; ///< Offset 1761 EwrdWiFiDynamicSarRangeSets
|
|
UINT8 EwrdWiFiSarTxPowerSet2Limit1; ///< Offset 1762 EwrdWiFiSarTxPowerSet2Limit1
|
|
UINT8 EwrdWiFiSarTxPowerSet2Limit2; ///< Offset 1763 EwrdWiFiSarTxPowerSet2Limit2
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|
UINT8 EwrdWiFiSarTxPowerSet2Limit3; ///< Offset 1764 EwrdWiFiSarTxPowerSet2Limit3
|
|
UINT8 EwrdWiFiSarTxPowerSet2Limit4; ///< Offset 1765 EwrdWiFiSarTxPowerSet2Limit4
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UINT8 EwrdWiFiSarTxPowerSet2Limit5; ///< Offset 1766 EwrdWiFiSarTxPowerSet2Limit5
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|
UINT8 EwrdWiFiSarTxPowerSet2Limit6; ///< Offset 1767 EwrdWiFiSarTxPowerSet2Limit6
|
|
UINT8 EwrdWiFiSarTxPowerSet2Limit7; ///< Offset 1768 EwrdWiFiSarTxPowerSet2Limit7
|
|
UINT8 EwrdWiFiSarTxPowerSet2Limit8; ///< Offset 1769 EwrdWiFiSarTxPowerSet2Limit8
|
|
UINT8 EwrdWiFiSarTxPowerSet2Limit9; ///< Offset 1770 EwrdWiFiSarTxPowerSet2Limit9
|
|
UINT8 EwrdWiFiSarTxPowerSet2Limit10; ///< Offset 1771 EwrdWiFiSarTxPowerSet2Limit10
|
|
UINT8 EwrdWiFiSarTxPowerSet3Limit1; ///< Offset 1772 EwrdWiFiSarTxPowerSet3Limit1
|
|
UINT8 EwrdWiFiSarTxPowerSet3Limit2; ///< Offset 1773 EwrdWiFiSarTxPowerSet3Limit2
|
|
UINT8 EwrdWiFiSarTxPowerSet3Limit3; ///< Offset 1774 EwrdWiFiSarTxPowerSet3Limit3
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|
UINT8 EwrdWiFiSarTxPowerSet3Limit4; ///< Offset 1775 EwrdWiFiSarTxPowerSet3Limit4
|
|
UINT8 EwrdWiFiSarTxPowerSet3Limit5; ///< Offset 1776 EwrdWiFiSarTxPowerSet3Limit5
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|
UINT8 EwrdWiFiSarTxPowerSet3Limit6; ///< Offset 1777 EwrdWiFiSarTxPowerSet3Limit6
|
|
UINT8 EwrdWiFiSarTxPowerSet3Limit7; ///< Offset 1778 EwrdWiFiSarTxPowerSet3Limit7
|
|
UINT8 EwrdWiFiSarTxPowerSet3Limit8; ///< Offset 1779 EwrdWiFiSarTxPowerSet3Limit8
|
|
UINT8 EwrdWiFiSarTxPowerSet3Limit9; ///< Offset 1780 EwrdWiFiSarTxPowerSet3Limit9
|
|
UINT8 EwrdWiFiSarTxPowerSet3Limit10; ///< Offset 1781 EwrdWiFiSarTxPowerSet3Limit10
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit1; ///< Offset 1782 EwrdWiFiSarTxPowerSet4Limit1
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit2; ///< Offset 1783 EwrdWiFiSarTxPowerSet4Limit2
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit3; ///< Offset 1784 EwrdWiFiSarTxPowerSet4Limit3
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit4; ///< Offset 1785 EwrdWiFiSarTxPowerSet4Limit4
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit5; ///< Offset 1786 EwrdWiFiSarTxPowerSet4Limit5
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit6; ///< Offset 1787 EwrdWiFiSarTxPowerSet4Limit6
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit7; ///< Offset 1788 EwrdWiFiSarTxPowerSet4Limit7
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit8; ///< Offset 1789 EwrdWiFiSarTxPowerSet4Limit8
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit9; ///< Offset 1790 EwrdWiFiSarTxPowerSet4Limit9
|
|
UINT8 EwrdWiFiSarTxPowerSet4Limit10; ///< Offset 1791 EwrdWiFiSarTxPowerSet4Limit10
|
|
UINT8 WgdsWiFiSarDeltaGroup1PowerMax1; ///< Offset 1792 WgdsWiFiSarDeltaGroup1PowerMax1
|
|
UINT8 WgdsWiFiSarDeltaGroup1PowerChainA1; ///< Offset 1793 WgdsWiFiSarDeltaGroup1PowerChainA1
|
|
UINT8 WgdsWiFiSarDeltaGroup1PowerChainB1; ///< Offset 1794 WgdsWiFiSarDeltaGroup1PowerChainB1
|
|
UINT8 WgdsWiFiSarDeltaGroup1PowerMax2; ///< Offset 1795 WgdsWiFiSarDeltaGroup1PowerMax2
|
|
UINT8 WgdsWiFiSarDeltaGroup1PowerChainA2; ///< Offset 1796 WgdsWiFiSarDeltaGroup1PowerChainA2
|
|
UINT8 WgdsWiFiSarDeltaGroup1PowerChainB2; ///< Offset 1797 WgdsWiFiSarDeltaGroup1PowerChainB2
|
|
UINT8 WgdsWiFiSarDeltaGroup2PowerMax1; ///< Offset 1798 WgdsWiFiSarDeltaGroup2PowerMax1
|
|
UINT8 WgdsWiFiSarDeltaGroup2PowerChainA1; ///< Offset 1799 WgdsWiFiSarDeltaGroup2PowerChainA1
|
|
UINT8 WgdsWiFiSarDeltaGroup2PowerChainB1; ///< Offset 1800 WgdsWiFiSarDeltaGroup2PowerChainB1
|
|
UINT8 WgdsWiFiSarDeltaGroup2PowerMax2; ///< Offset 1801 WgdsWiFiSarDeltaGroup2PowerMax2
|
|
UINT8 WgdsWiFiSarDeltaGroup2PowerChainA2; ///< Offset 1802 WgdsWiFiSarDeltaGroup2PowerChainA2
|
|
UINT8 WgdsWiFiSarDeltaGroup2PowerChainB2; ///< Offset 1803 WgdsWiFiSarDeltaGroup2PowerChainB2
|
|
UINT8 WgdsWiFiSarDeltaGroup3PowerMax1; ///< Offset 1804 WgdsWiFiSarDeltaGroup3PowerMax1
|
|
UINT8 WgdsWiFiSarDeltaGroup3PowerChainA1; ///< Offset 1805 WgdsWiFiSarDeltaGroup3PowerChainA1
|
|
UINT8 WgdsWiFiSarDeltaGroup3PowerChainB1; ///< Offset 1806 WgdsWiFiSarDeltaGroup3PowerChainB1
|
|
UINT8 WgdsWiFiSarDeltaGroup3PowerMax2; ///< Offset 1807 WgdsWiFiSarDeltaGroup3PowerMax2
|
|
UINT8 WgdsWiFiSarDeltaGroup3PowerChainA2; ///< Offset 1808 WgdsWiFiSarDeltaGroup3PowerChainA2
|
|
UINT8 WgdsWiFiSarDeltaGroup3PowerChainB2; ///< Offset 1809 WgdsWiFiSarDeltaGroup3PowerChainB2
|
|
UINT8 Reserved19[32]; ///< Offset 1810:1841
|
|
// Reserved for Groups 4 to 9, each needs 6 bytes and total 36 bytes reserved
|
|
UINT8 WiFiDynamicSarAntennaACurrentSet; ///< Offset 1842 WiFiDynamicSarAntennaACurrentSet
|
|
UINT8 WiFiDynamicSarAntennaBCurrentSet; ///< Offset 1843 WiFiDynamicSarAntennaBCurrentSet
|
|
UINT8 BluetoothSar; ///< Offset 1844 BluetoothSar
|
|
UINT8 BluetoothSarBr; ///< Offset 1845 BluetoothSarBr
|
|
UINT8 BluetoothSarEdr2; ///< Offset 1846 BluetoothSarEdr2
|
|
UINT8 BluetoothSarEdr3; ///< Offset 1847 BluetoothSarEdr3
|
|
UINT8 BluetoothSarLe; ///< Offset 1848 BluetoothSarLe
|
|
UINT8 Reserved20[4]; ///< Offset 1849:1852
|
|
// Reserved for Bluetooth Sar future use
|
|
UINT8 CoExistenceManager; ///< Offset 1853 CoExistenceManager
|
|
UINT8 RunTimeVmControl; ///< Offset 1854 RunTime VM Control
|
|
//
|
|
//Feature Specific Data Bits
|
|
//
|
|
UINT8 UsbTypeCSupport; ///< Offset 1855 USB Type C Supported
|
|
UINT32 HebcValue; ///< Offset 1856 HebcValue
|
|
UINT8 PcdBatteryPresent; ///< Offset 1860 Battery Present - Bit0: Real Battery is supported on this platform. Bit1: Virtual Battery is supported on this platform.
|
|
UINT8 PcdTsOnDimmTemperature; ///< Offset 1861 TS-on-DIMM temperature
|
|
UINT8 Reserved21[3]; ///< Offset 1862:1864
|
|
UINT8 PcdRealBattery1Control; ///< Offset 1865 Real Battery 1 Control
|
|
UINT8 PcdRealBattery2Control; ///< Offset 1866 Real Battery 2 Control
|
|
UINT8 PcdMipiCamSensor; ///< Offset 1867 Mipi Camera Sensor
|
|
UINT8 PcdNCT6776FCOM; ///< Offset 1868 NCT6776F COM
|
|
UINT8 PcdNCT6776FSIO; ///< Offset 1869 NCT6776F SIO
|
|
UINT8 PcdNCT6776FHWMON; ///< Offset 1870 NCT6776F HWMON
|
|
UINT8 PcdH8S2113SIO; ///< Offset 1871 H8S2113 SIO
|
|
UINT8 PcdZPoddConfig; ///< Offset 1872 ZPODD
|
|
UINT8 PcdRGBCameraAdr; ///< Offset 1873 RGB Camera Address
|
|
UINT8 PcdDepthCameraAdr; ///< Offset 1874 Depth Camera Addresy
|
|
UINT32 PcdSmcRuntimeSciPin; ///< Offset 1875 SMC Runtime Sci Pin
|
|
UINT8 PcdConvertableDockSupport; ///< Offset 1879 Convertable Dock Support
|
|
UINT8 PcdEcHotKeyF3Support; ///< Offset 1880 Ec Hotkey F3 Support
|
|
UINT8 PcdEcHotKeyF4Support; ///< Offset 1881 Ec Hotkey F4 Support
|
|
UINT8 PcdEcHotKeyF5Support; ///< Offset 1882 Ec Hotkey F5 Support
|
|
UINT8 PcdEcHotKeyF6Support; ///< Offset 1883 Ec Hotkey F6 Support
|
|
UINT8 PcdEcHotKeyF7Support; ///< Offset 1884 Ec Hotkey F7 Support
|
|
UINT8 PcdEcHotKeyF8Support; ///< Offset 1885 Ec Hotkey F8 Support
|
|
UINT8 PcdVirtualButtonVolumeUpSupport; ///< Offset 1886 Virtual Button Volume Up Support
|
|
UINT8 PcdVirtualButtonVolumeDownSupport; ///< Offset 1887 Virtual Button Volume Down Support
|
|
UINT8 PcdVirtualButtonHomeButtonSupport; ///< Offset 1888 Virtual Button Home Button Support
|
|
UINT8 PcdVirtualButtonRotationLockSupport; ///< Offset 1889 Virtual Button Rotation Lock Support
|
|
UINT8 PcdSlateModeSwitchSupport; ///< Offset 1890 Slate Mode Switch Support
|
|
UINT8 PcdVirtualGpioButtonSupport; ///< Offset 1891 Virtual Button Support
|
|
UINT8 PcdAcDcAutoSwitchSupport; ///< Offset 1892 Ac Dc Auto Switch Support
|
|
UINT32 PcdPmPowerButtonGpioPin; ///< Offset 1893 Pm Power Button Gpio Pin
|
|
UINT8 PcdAcpiEnableAllButtonSupport; ///< Offset 1897 Acpi Enable All Button Support
|
|
UINT8 PcdAcpiHidDriverButtonSupport; ///< Offset 1898 Acpi Hid Driver Button Support
|
|
UINT8 DisplayDepthLowerLimit; ///< Offset 1899 DPTF Display Depth Lower Limit in percent
|
|
UINT8 DisplayDepthUpperLimit; ///< Offset 1900 DPTF Display Depth Upper Limit in percent
|
|
UINT8 PepWiGigF1; ///< Offset 1901 PEP F1 constraints for WiGig device
|
|
UINT8 ThermalSamplingPeriodWrls; ///< Offset 1902 ThermalSamplingPeriodWrls
|
|
UINT32 EcLowPowerModeGpioPin; ///< Offset 1903 EcLowPowerModeGpioPin
|
|
UINT32 EcSmiGpioPin; ///< Offset 1907 EcSmiGpioPin
|
|
UINT8 WakeOnWiGigSupport; ///< Offset 1911 Wake on S3-S4 WiGig Docking Support
|
|
//
|
|
// UCMC setup option, GPIO Pad
|
|
//
|
|
UINT8 UCMS; ///< Offset 1912 Option to select UCSI/UCMC device
|
|
UINT32 UcmcPort1Gpio; ///< Offset 1913 Gpio for UCMC Port 1 Interrupt
|
|
UINT32 UcmcPort2Gpio; ///< Offset 1917 Gpio for UCMC Port 2 Interrupt
|
|
UINT8 Reserved22[24]; ///< Offset 1921:1944
|
|
UINT8 EnablePchFivrParticipant; ///< Offset 1945 EnablePchFivrParticipant
|
|
UINT8 Reserved23[5]; ///< Offset 1946:1950
|
|
UINT8 SerialPortAcpiDebug; ///< Offset 1951 Serial Port ACPI debug
|
|
UINT8 Ufp2DfpGlobalFlag; ///< Offset 1952 Upstream Facing port or Downstream Facing port Global Flag from LPC EC
|
|
UINT8 Ufp2DfpUsbPort; ///< Offset 1953 Upstream Facing port or Downstream Facing port number from LPC EC
|
|
UINT8 DbcGlobalFlag; ///< Offset 1954 Debug Mode Global Flag from LPC EC
|
|
UINT8 DbcUsbPort; ///< Offset 1955 Debug Mode USB Port Number from LPC EC
|
|
UINT8 TotalTypeCPorts; ///< Offset 1956 Total Number of type C ports that are supported by platform
|
|
UINT8 UsbTypeCPort1; ///< Offset 1957 Type C Connector 1 Port mapping within the controller the port exposed
|
|
UINT8 UsbTypeCPort1Pch; ///< Offset 1958 Type C Connector 1 Port mapping within the PCH controller (If Split mode supported)
|
|
UINT8 UsbCPort1Proterties; ///< Offset 1959 Type C Connector 1 Portperties Split Support/Controller(PCH/TBT/CPU)/Root port (vaild for TBT)
|
|
UINT8 UsbTypeCPort2; ///< Offset 1960 Type C Connector 2 Port mapping within the controller the port exposed
|
|
UINT8 UsbTypeCPort2Pch; ///< Offset 1961 Type C Connector 2 Port mapping within the PCH controller (If Split mode supported)
|
|
UINT8 UsbCPort2Proterties; ///< Offset 1962 Type C Connector 2 Portperties Split Support/Controller(PCH/TBT/CPU)/Root port (vaild for TBT)
|
|
UINT8 UsbTypeCPort3; ///< Offset 1963 Type C Connector 3 Port mapping within the controller the port exposed
|
|
UINT8 UsbTypeCPort3Pch; ///< Offset 1964 Type C Connector 3 Port mapping within the PCH controller (If Split mode supported)
|
|
UINT8 UsbCPort3Proterties; ///< Offset 1965 Type C Connector 3 Portperties Split Support/Controller(PCH/TBT/CPU)/Root port (vaild for TBT)
|
|
UINT8 UsbTypeCPort4; ///< Offset 1966 Type C Connector 4 Port mapping within the controller the port exposed
|
|
UINT8 UsbTypeCPort4Pch; ///< Offset 1967 Type C Connector 4 Port mapping within the PCH controller (If Split mode supported)
|
|
UINT8 UsbCPort4Proterties; ///< Offset 1968 Type C Connector 4 Portperties Split Support/Controller(PCH/TBT/CPU)/Root port (vaild for TBT)
|
|
UINT8 UsbTypeCPort5; ///< Offset 1969 Type C Connector 5 Port mapping within the controller the port exposed
|
|
UINT8 UsbTypeCPort5Pch; ///< Offset 1970 Type C Connector 5 Port mapping within the PCH controller (If Split mode supported)
|
|
UINT8 UsbCPort5Proterties; ///< Offset 1971 Type C Connector 5 Portperties Split Support/Controller(PCH/TBT/CPU)/Root port (vaild for TBT)
|
|
UINT8 UsbTypeCPort6; ///< Offset 1972 Type C Connector 6 Port mapping within the controller the port exposed
|
|
UINT8 UsbTypeCPort6Pch; ///< Offset 1973 Type C Connector 6 Port mapping within the PCH controller (If Split mode supported)
|
|
UINT8 UsbCPort6Proterties; ///< Offset 1974 Type C Connector 6 Portperties Split Support/Controller(PCH/TBT/CPU)/Root port (vaild for TBT)
|
|
UINT8 AntennaDiversity; ///< Offset 1975 AntennaDiversity
|
|
UINT8 BluetoothSarLe2Mhz; ///< Offset 1976 BluetoothSarLe2Mhz
|
|
UINT8 BluetoothSarLeLr; ///< Offset 1977 BluetoothSarLeLr
|
|
} PLATFORM_NVS_AREA;
|
|
|
|
#pragma pack(pop)
|
|
#endif
|