112 lines
8.5 KiB
C
112 lines
8.5 KiB
C
/** @file
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GPIO definition table for Tigerlake Simics
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Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _TIGERLAKE_SIMICS_GPIO_TABLE_H_
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#define _TIGERLAKE_SIMICS_GPIO_TABLE_H_
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#include <Pins/GpioPinsVer2Lp.h>
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#include <Library/GpioLib.h>
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#include <Library/GpioConfig.h>
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///
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/// !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
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/// Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
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/// Configuring pins to native function in GPIO table would override the pin settings resulting in unexpected behavior.
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///
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static GPIO_INIT_CONFIG mGpioTableTglSimics[] =
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{
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// CPU M.2 SSD
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{GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD PWREN
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{GPIO_VER2_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD RESET
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// M.2 Key-E - WLAN/BT
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{GPIO_VER2_LP_GPP_A13, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // BT_RF_KILL_N
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{GPIO_VER2_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // WIFI_RF_KILL_N
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{GPIO_VER2_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // WLAN_RST_N
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// All SCI GPIO's are not programmed due to HFPGA issue : 1505908653
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// {GPIO_VER2_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIFI_WAKE_N
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// {GPIO_VER2_LP_GPP_H19, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //UART_BT_WAKE_N : Not default POR
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// X4 Pcie Slot for Gen3 and Gen 4
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{GPIO_VER2_LP_GPP_A14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_PCIE_SLOT1_PWREN_N
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{GPIO_VER2_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_PCIE_SLOT1_RESET_N
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// {GPIO_VER2_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //ONBOARD_X4_PCIE_SLOT1_WAKE_N
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{GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_PCIE_SLOT1_DGPU_SEL
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{GPIO_VER2_LP_GPP_F21, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_PCIE_SLOT1_DGPU_PWROK
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// TBT Re-Timers
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{GPIO_VER2_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //TC_RETIMER_FORCE_PWR
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{GPIO_VER2_LP_GPD7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioDswReset, GpioTermNone}}, //TCP_RETIMER_PERST_N
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// Battery Charger Vmin to PCH PROCHOT, derived from TGL
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// {GPIO_VER2_LP_GPP_B2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntEdge|GpioIntSci,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //BC_PROCHOT_N
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// SATA Direct Connect
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{GPIO_VER2_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //SATA_DIRECT_PWREN
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// FPS
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{GPIO_VER2_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //FPS_RST_N
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{GPIO_VER2_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //FPS_INT
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// PCH M.2 SSD
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{GPIO_VER2_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_PWREN
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{GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_N
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// Camera
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{GPIO_VER2_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CRD_CAM_PWREN - CAM1
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{GPIO_VER2_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WF_CAM_RST_N - CAM1
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{GPIO_VER2_LP_GPP_R6, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM2_PWREN/BIOS_REC
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{GPIO_VER2_LP_GPP_H12, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM2_RST_N
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{GPIO_VER2_LP_GPP_H15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM3_PWREN
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{GPIO_VER2_LP_GPP_H13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM3_RST_N
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// Camera Common GPIO's for all Camera, Rework Options
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{GPIO_VER2_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CRD_CAM_STROBE_1
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{GPIO_VER2_LP_GPP_R5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CRD_CAM_PRIVACY_LED_1
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{GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WF_CAM_CLK_EN
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// Audio
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{GPIO_VER2_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //SPKR_PD_N
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{GPIO_VER2_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, // CODEC_INT_N
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// Touch Pad
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// Touch Pad and Touch Panel 2 share the same Power Enable, default is Touch pad
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{GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //TCH_PAD_LS_EN - PWR_En
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{GPIO_VER2_LP_GPP_C8, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault,GpioIntEdge|GpioIntApic,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //TCH_PAD_INT_N
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// EC
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// {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N
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{GPIO_VER2_LP_GPP_E8, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_CS_N
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// SPI TPM, derived from TGL
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// {GPIO_VER2_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //SPI_TPM_INT_N
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// TypeC BIAS : Not used by default in RVP, derived from TGL
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{GPIO_VER2_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //DISP_AUX_P_BIAS_GPIO
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{GPIO_VER2_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //DISP_AUX_N_BIAS_GPIO
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// LAN : Not used by Default in RVP
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{GPIO_VER2_LP_GPP_F7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //LAN_RST_N
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// X1 Pcie Slot
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{GPIO_VER2_LP_GPP_H2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //X1 Slot PWREN
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// {GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //X1 Slot WAKE
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{GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //X1 Slot RESET
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};
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#endif // _TIGERLAKE_SIMICS_GPIO_TABLE_H_
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