179 lines
10 KiB
C
179 lines
10 KiB
C
/** @file
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GPIO definition table for Tigerlake Simics
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Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _TIGERLAKE_SIMICS_SPD_TABLE_H_
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#define _TIGERLAKE_SIMICS_SPD_TABLE_H_
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//
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// DQByteMap[0] - ClkDQByteMap:
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// If clock is per rank, program to [0xFF, 0xFF]
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// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
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// If clock is shared by 2 ranks but does not go to all bytes,
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// Entry[i] defines which DQ bytes Group i services
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// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
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// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
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// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
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// For DDR, DQByteMap[3:1] = [0xFF, 0]
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// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
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// Variable only exists to make the code easier to use
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// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
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// Variable only exists to make the code easier to use
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//
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//
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// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3 and CNL MRC
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//
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSklRvp3[2][6][2] = {
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// Channel 0:
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{
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{ 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
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{ 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
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{ 0xFF, 0x00 }, // CTL (CS) goes to all bytes
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{ 0x00, 0x00 }, // Unused in CNL MRC
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{ 0x00, 0x00 }, // Unused in CNL MRC
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{ 0x00, 0x00 }, // Unused in CNL MRC
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},
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// Channel 1:
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{
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{ 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[0,1,4,5], CLK1 goes to package 1 - Bytes[2,3,6,7]
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{ 0x33, 0xCC }, // Cmd CAA goes to Bytes[0,1,4,5], Cmd CAB goes to Bytes[2,3,6,7]
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{ 0xFF, 0x00 }, // CTL (CS) goes to all bytes
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{ 0x00, 0x00 }, // Unused in CNL MRC
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{ 0x00, 0x00 }, // Unused in CNL MRC
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{ 0x00, 0x00 }, // Unused in CNL MRC
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}
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};
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//
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// DQS byte swizzling between CPU and DRAM - for SKL RVP1, RVP3, RVP13
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//
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp3[2][8] = {
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{ 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0
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{ 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1
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};
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// LPDDR4 200b 8Gb die, DDP
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// Samsung K4F6E304Hx-MGCH
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// Hynix H9HCNNNBUUxLHR-NLx
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// Micron MT53B512M32D2NP-062
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// 3200, 28-29-29-68
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// 2 ranks per channel, 2 SDRAMs per rank, 4x8Gb = 4GB total per channel
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4Ddp8Gb200bSpd[] = {
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0x23, ///< 0 384 SPD bytes used, 512 total
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0x10, ///< 1 SPD Revision 1.0
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0x10, ///< 2 DRAM Type: LPDDR4 SDRAM
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0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
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0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density
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0x19, ///< 5 15 Rows, 10 Columns
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0x95, ///< 6 Non-Monolithic DRAM Device, 2 die, 2 Channels per package, Signal Loading Matrix 1
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0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
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0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
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0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
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0x00, ///< 10 Reserved
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0x00, ///< 11 Module Nominal Voltage: Reserved
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0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel
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0x22, ///< 13 Module Memory Bus width: 2 Channels, 32 bits channel width, no ECC
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0x00, ///< 14 Module Thermal Sensor: none
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0x00, ///< 15 Extended Module Type: Reserved
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0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
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0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
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0x05, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200)
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0xFF, ///< 19 tCKAVGmax = 32.002 ns
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0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
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0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16
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0x00, ///< 22 CAS Latencies supported (Third Byte) :
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0x00, ///< 23 CAS Latencies supported (Fourth Byte):
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0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns
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0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
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0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
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0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
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0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
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0xA0, ///< 29 tRFCab = 180 ns (8 Gb)
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0x05, ///< 30 tRFCab MSB
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0xD0, ///< 31 tRFCpb = 90 ns (8 Gb)
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0x02, ///< 32 tRFCpb MSB
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0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
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0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
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0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
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0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
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0x00, ///< 123 FTB for tAAmin = 17.5 ns
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0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns
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0x00, ///< 125 FTB for tCKAVGmin = 0.625 ns (LPDDR4-3200)
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0x00, ///< 126 CRC A
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0x00, ///< 127 CRC B
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0, 0, ///< 128 - 129
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
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0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
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0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
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0x00, ///< 322 Module Manufacturing Location
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0x00, ///< 323 Module Manufacturing Date Year
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0x00, ///< 324 Module Manufacturing Date Week
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0x55, ///< 325 Module Serial Number A
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0x00, ///< 326 Module Serial Number B
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0x00, ///< 327 Module Serial Number C
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0x00, ///< 328 Module Serial Number D
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0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
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0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
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0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
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0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
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0x00, ///< 349 Module Revision Code
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0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
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0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
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0x00, ///< 352 DRAM Stepping
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0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
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0, 0 ///< 510 - 511
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};
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#endif // _TIGERLAKE_SIMICS_SPD_TABLE_H_
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