233 lines
9.0 KiB
Plaintext
233 lines
9.0 KiB
Plaintext
## @file
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# Platform description.
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#
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# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.<BR>
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#
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# This program and the accompanying materials are licensed and made available under
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# the terms and conditions of the BSD License which accompanies this distribution.
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# The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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##
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################################################################################
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#
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# Pcd Section - list of all EDK II PCD Entries defined by this Platform
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#
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################################################################################
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[PcdsFeatureFlag.common]
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
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[PcdsFixedAtBuild.common]
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gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
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!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
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gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
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!endif
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase|0x80000000
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xC0000000
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xC0000000
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gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
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gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
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gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
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gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00024000
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gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x6000
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gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
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gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
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!if $(TARGET) == RELEASE
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
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!else
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
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!endif
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gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
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gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
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gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
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#
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# 8MB Default
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#
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gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
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#
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# 16MB TSEG in Debug build only.
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#
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!if $(TARGET) == DEBUG
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gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
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!endif
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
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!if $(TARGET) == RELEASE
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
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!else
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
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!endif
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
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!if $(TARGET) == RELEASE
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
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!else
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
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!endif
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#
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# FSP Binary base address will be set in FDF basing on flash map
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
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## Specifies max supported number of Logical Processors.
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# @Prompt Configure max supported number of Logical Processorss
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12
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## Specifies the size of the microcode Region.
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# @Prompt Microcode Region size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
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## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
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# @Prompt Timeout for the BSP to detect all APs for the first time.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
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## Specifies the AP wait loop state during POST phase.
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# The value is defined as below.
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# 1: Place AP in the Hlt-Loop state.
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# 2: Place AP in the Mwait-Loop state.
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# 3: Place AP in the Run-Loop state.
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# @Prompt The AP wait loop state.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
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#
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# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
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#
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# BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
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# BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
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# that lie entirely within the expected fixed memory regions.
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# BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
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# BIT3-31: Reserved
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#
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gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
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# Do not support output status code to memory
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
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[PcdsFixedAtBuild.IA32]
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gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
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gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
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gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
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gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
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[PcdsFixedAtBuild.X64]
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gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8
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# Default platform supported RFC 4646 languages: (American) English
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gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
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[PcdsPatchableInModule.common]
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0304
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gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
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!if $(TARGET) == DEBUG
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gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
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!endif
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[PcdsDynamicHii.X64.DEFAULT]
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gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
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gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
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!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
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gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
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!endif
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[PcdsDynamicDefault]
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#
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# FSP Binary base address will be set in FDF basing on flash map
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
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!if $(TARGET) == RELEASE
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
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!else
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
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!endif
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[PcdsDynamicDefault.common.DEFAULT]
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gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
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#
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# Set video to native resolution as Windows 8 WHCK requirement.
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#
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE
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## Specifies the AP wait loop state during POST phase.
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# The value is defined as below.
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# 1: Place AP in the Hlt-Loop state.
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# 2: Place AP in the Mwait-Loop state.
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# 3: Place AP in the Run-Loop state.
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# @Prompt The AP wait loop state.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
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## Specifies the AP target C-state for Mwait during POST phase.
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# The default value 0 means C1 state.
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# The value is defined as below.<BR><BR>
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# @Prompt The specified AP target C-state for Mwait.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
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gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
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