233 lines
8.3 KiB
C
233 lines
8.3 KiB
C
/** @file
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;******************************************************************************
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;* Copyright 2021 Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corp.
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;*
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;******************************************************************************
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*/
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/** @file
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@copyright
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INTEL CONFIDENTIAL
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Copyright (c) 2013 - 2021 Intel Corporation. All rights reserved
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CMOSMAP_H_
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#define _CMOSMAP_H_
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//
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// GENERAL USAGE GUIDELINES
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//
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/**
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CMOS 0x00 - 0x0F are used by RTC. defined in ICHx spec
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CMOS 0x10 - 0x7F are reserved for board specific use by Intel
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CMOS 0x80 - 0xFF are reserved for OEM use only
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*/
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#define CmosIo_70 0x70
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#define CmosIo_71 0x71
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#define CmosIo_72 0x72
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#define CmosIo_73 0x73
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//
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// PLATFORM SPECIFIC USAGE
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//
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#define FIT_REC_TXT_POLICY_TYPE_A 0x2A
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// gino: insyde dont use Intel CMOS offset. remove this for build error:\AlderLake\AlderLakeChipsetPkg\Include\ChipsetCmos.h(101): error C2059: syntax error: 'constant' >>
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// #define RTC_ADDRESS_CENTURY 0x32
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// gino: insyde dont use Intel CMOS offset <<
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#define CPU_HT_POLICY 0x50
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#define CPU_HT_POLICY_ENABLED 0x01
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#define TPM_POLICY 0x60
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#define TPM_POLICY_ENABLED 0x01
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#define CMOS_TBTHR_PRESENT_ON_RESUME 0x58
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#define CMOS_CPV_STATE 0x6A
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// gino: insyde dont use Intel CMOS offset >>
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// #define CMOS_TXT_REG 0x6D
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// gino: insyde dont use Intel CMOS offset <<
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#define CMOS_TXT_REG1 0x7F
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#define CMOS_PLATFORM_RESET_OS 0x80
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#define CMOS_CPU_BSP_SELECT 0x90
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// gino: insyde dont use Intel CMOS offset >>
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// #define CMOS_CPU_RATIO_OFFSET 0x92
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// #define CMOS_ICH_PORT80_OFFSET 0x97
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// gino: insyde dont use Intel CMOS offset <<
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#define CMOS_OC_S3_SCRATCHPAD 0x98
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// gino: insyde dont use Intel CMOS offset >>
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// #define CMOS_OC_SEND_BCLK_RAMP_MSG 0x99
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// gino: insyde dont use Intel CMOS offset <<
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#define CMOS_DATA_PORT 0x71
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#define CMOS_ADDR_PORT 0x70
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#define CMOS_BAD_REG 0xe
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#define CMOS_MAXRATIO_CONFIG_REG 0xEF
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#define CMOS_FFS_NV_HASH00_DATA_REG 0x91
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#define CMOS_FFS_NV_HASH01_DATA_REG 0x81
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#define CMOS_FFS_NV_HASH02_DATA_REG 0x82
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#define CMOS_FFS_NV_HASH03_DATA_REG 0x83
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#define CMOS_FFS_NV_HASH04_DATA_REG 0x84
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#define CMOS_FFS_NV_HASH05_DATA_REG 0x85
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#define CMOS_FFS_NV_HASH06_DATA_REG 0x86
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#define CMOS_FFS_NV_HASH07_DATA_REG 0x87
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#define CMOS_FFS_NV_HASH08_DATA_REG 0x88
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#define CMOS_FFS_NV_HASH09_DATA_REG 0x89
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#define CMOS_FFS_NV_HASH10_DATA_REG 0x8a
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#define CMOS_FFS_NV_HASH11_DATA_REG 0x8b
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#define CMOS_FFS_NV_HASH12_DATA_REG 0x8c
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#define CMOS_FFS_NV_HASH13_DATA_REG 0x8d
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#define CMOS_FFS_NV_HASH14_DATA_REG 0x8e
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#define CMOS_FFS_NV_HASH15_DATA_REG 0x8f
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#define CMOS_FFS_NV_HASH16_DATA_REG 0xd0
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#define CMOS_FFS_NV_HASH17_DATA_REG 0xd1
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#define CMOS_FFS_NV_HASH18_DATA_REG 0xd2
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#define CMOS_FFS_NV_HASH19_DATA_REG 0xd3
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#define CMOS_FFS_NV_HASH20_DATA_REG 0xd4
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#define CMOS_FFS_NV_HASH21_DATA_REG 0xd5
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#define CMOS_FFS_NV_HASH22_DATA_REG 0xd6
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#define CMOS_FFS_NV_HASH23_DATA_REG 0xd7
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#define CMOS_FFS_NV_HASH24_DATA_REG 0xd8
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#define CMOS_FFS_NV_HASH25_DATA_REG 0xd9
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#define CMOS_FFS_NV_HASH26_DATA_REG 0xda
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#define CMOS_FFS_NV_HASH27_DATA_REG 0xdb
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#define CMOS_FFS_NV_HASH28_DATA_REG 0xdc
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#define CMOS_FFS_NV_HASH29_DATA_REG 0xdd
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#define CMOS_FFS_NV_HASH30_DATA_REG 0xde
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#define CMOS_FFS_NV_HASH31_DATA_REG 0xdf
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#define CMOS_FFS_NV_CRITBATT_OVERRIDE_REG 0xFB
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#define CMOS_FFS_NV_FLAG_REG 0xBB
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#define CMOS_FFS_NV_CONFIG_REG 0x51
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#define CMOS_FFS_SCRAMBLER_SEED_REG0 0x41 // 16 bits
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#define CMOS_FFS_SCRAMBLER_SEED_REG1 0x42 // 16 bits
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#define CMOS_SERIAL_BAUD_RATE_REG 0x43
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#define CMOS_SERIAL_BAUD_RATE_1_REG 0x44
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#define CMOS_SERIAL_BAUD_RATE_2_REG 0x45
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#define CMOS_SERIAL_BAUD_RATE_3_REG 0x46
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#define CMOS_BOOT_REGISTER_REG 0x47
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//
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// USB4 platform settings
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//
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//[-start-210527-IB16740141-remove]//
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//
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// Redefine into CMOS_USB4_CM_MODE_REG_CHP in ChipsetCmos.h
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// To avoid CMOS_USB4_CM_MODE_REG conflicted with the settings of OEM Reserve in ChipsetCmos.h
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//
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//#define CMOS_USB4_CM_MODE_REG 0xF2
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//[-end-210527-IB16740141-remove]//
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#define CMOS_USB4_CM_MODE_DEFAULT_VALUE 1
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//
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// Debug Mask saved in CMOS
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//
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#define CMOS_DEBUG_PRINT_LEVEL_REG 0x4C
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#define CMOS_DEBUG_PRINT_LEVEL_1_REG 0x4D
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#define CMOS_DEBUG_PRINT_LEVEL_2_REG 0x4E
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#define CMOS_DEBUG_PRINT_LEVEL_3_REG 0x4F
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//
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// USB debug port config
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//
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#define USB_DEBUG_PORT_BUS_REG 0x51
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#define USB_DEBUG_PORT_DEVICE_REG 0x52
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#define USB_DEBUG_PORT_FUNCTION_REG 0x53
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#define USB_DEBUG_PORT_TEMP_RAM_REG 0x54
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#define USB_DEBUG_PORT_TEMP_RAM_1_REG 0x55
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#define USB_DEBUG_PORT_TEMP_RAM_2_REG 0x56
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#define USB_DEBUG_PORT_TEMP_RAM_3_REG 0x57
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//
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// USB3 debug port config
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//
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#define USB3_DEBUG_PORT_BUS_REG 0x59
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#define USB3_DEBUG_PORT_DEVICE_REG 0x5A
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#define USB3_DEBUG_PORT_FUNCTION_REG 0x5B
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#define USB3_DEBUG_XHC_MODE 0x5C
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#define CMOS_DEBUG_PRINT_ENDPOINTS 0x5E
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#define CMOS_FAST_BOOT_REG 0x6B
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#define OEM_SSP_FREE_REG_B4 0xB4
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#define OEM_SSP_FREE_REG_B5 0xB5
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#define OEM_SSP_FREE_REG_B6 0xB6
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#define OEM_SSP_FREE_REG_B7 0xB7
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#define OEM_SSP_FREE_REG_B8 0xB8
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#define OEM_SSP_FREE_REG_B9 0xB9
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#define OEM_SSP_FREE_REG_BA 0xBA
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#define OEM_SSP_FREE_REG_BB 0xBB
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#define OEM_SSP_FREE_REG_BC 0xBC
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#define OEM_SSP_FREE_REG_BD 0xBD
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#define OEM_SSP_FREE_REG_BE 0xBE
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#define OEM_SSP_FREE_REG_BF 0xBF
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#define SSP_PCH_BIOS_CMOS_REG_D0 0xD0
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#define SSP_PCH_BIOS_CMOS_REG_D1 0xD1
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#define SSP_PCH_BIOS_CMOS_REG_D2 0xD2
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#define SSP_PCH_BIOS_CMOS_REG_D3 0xD3
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#define SSP_PCH_BIOS_CMOS_REG_D4 0xD4
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#define SSP_PCH_BIOS_CMOS_REG_D5 0xD5
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#define SSP_PCH_BIOS_CMOS_REG_D6 0xD6
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#define SSP_PCH_BIOS_CMOS_REG_D7 0xD7
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#define SSP_PCH_BIOS_CMOS_REG_D8 0xD8
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#define SSP_PCH_BIOS_CMOS_REG_D9 0xD9
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#define SSP_PCH_BIOS_CMOS_REG_DA 0xDA
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#define SSP_PCH_BIOS_CMOS_REG_DB 0xDB
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#define SSP_PCH_BIOS_CMOS_REG_DC 0xDC
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#define SSP_PCH_BIOS_CMOS_REG_DD 0xDD
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#define SSP_PCH_BIOS_CMOS_REG_DE 0xDE
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#define SSP_PCH_BIOS_CMOS_REG_DF 0xDF
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#define OEM_SSP_FREE_REG_F3 0xF3
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#define OEM_SSP_FREE_REG_F4 0xF4
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#define OEM_SSP_FREE_REG_F5 0xF5
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#define OEM_SSP_FREE_REG_F6 0xF6
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#define OEM_SSP_FREE_REG_F7 0xF7
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#define DEFAULT_VALUE 0
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#endif
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