189 lines
7.5 KiB
C
189 lines
7.5 KiB
C
/** @file
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This is file contain Opregion definition for DG.
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Software SCI interface between system BIOS, ASL code, and Graphics drivers.
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;******************************************************************************
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;* Copyright (c) 2021, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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- OpRegion / Software SCI SPEC
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**/
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#ifndef _DG_OPREGION_H_
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#define _DG_OPREGION_H_
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#define DG_HEADER_SIGNATURE "IntelGraphicsMem"
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//[-start-211123-QINGLIN0117-modify]//
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#ifdef LCFC_SUPPORT
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#define HEADER_OPREGION_VER 0x0203
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#else
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#define HEADER_OPREGION_VER 0x0202
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#endif
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//[-end-211123-QINGLIN0117-modify]//
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#define HEADER_SIZE 0x2000
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#define HEADER_OPREGION_REV 0x00
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#define HD_MBOX1 BIT0
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#define HD_MBOX2 BIT1
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#define HD_MBOX3 BIT2
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#define HD_MBOX4 BIT3
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#define HD_MBOX5 BIT4
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#define HEADER_MBOX_SUPPORT (HD_MBOX5 + HD_MBOX4 + HD_MBOX3 + HD_MBOX1)
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#define BACKLIGHT_BRIGHTNESS 0xFF
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#define INIT_BRIGHT_LEVEL 0x64
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#define FIELD_VALID_BIT BIT31
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#define WORD_FIELD_VALID_BIT BIT15
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/**
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OpRegion structures:
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Sub-structures define the different parts of the OpRegion followed by the
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main structure representing the entire OpRegion.
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@note These structures are packed to 1 byte offsets because the exact
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data location is required by the supporting design specification due to
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the fact that the data is used by ASL and Graphics driver code compiled
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separately.
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**/
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#pragma pack(1)
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///
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/// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to
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/// identify a block of memory as the graphics driver OpRegion.
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/// Offset 0x0, Size 0x100
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///
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typedef struct {
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CHAR8 SIGN[0x10]; ///< Offset 0x00 OpRegion Signature
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UINT32 SIZE; ///< Offset 0x10 OpRegion Size
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UINT32 OVER; ///< Offset 0x14 OpRegion Structure Version
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UINT8 SVER[0x20]; ///< Offset 0x18 System BIOS Build Version
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UINT8 VVER[0x10]; ///< Offset 0x38 Video BIOS Build Version
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UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version
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UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes
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UINT32 DMOD; ///< Offset 0x5C Driver Model
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UINT32 PCON; ///< Offset 0x60 Platform Configuration
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CHAR16 DVER[0x10]; ///< Offset 0x64 GOP Version
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UINT8 RM01[0x7C]; ///< Offset 0x84 Reserved Must be zero
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} DG_OPREGION_HEADER;
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///
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/// OpRegion Mailbox 1 - Public ACPI Methods
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/// Offset 0x100, Size 0x100
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///
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typedef struct {
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UINT8 RSVD[0x100]; ///< Offset 0x100 - 0x1FF BIOS does not uses this section of OpRegion
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} DG_OPREGION_MBOX1;
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///
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/// OpRegion Mailbox 2 - Software SCI Interface
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/// Offset 0x200, Size 0x100
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///
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typedef struct {
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UINT8 UNUSED[0x100]; ///< Offset 0x200 - 0x2FF Obselete in DG
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} DG_OPREGION_MBOX2;
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///
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/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support
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/// Offset 0x300, Size 0x100
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///
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typedef struct {
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UINT32 ARDY; ///< Offset 0x300 Driver Readiness
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UINT32 ASLC; ///< Offset 0x304 ASLE Interrupt Command / Status
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UINT32 TCHE; ///< Offset 0x308 Technology Enabled Indicator
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UINT32 ALSI; ///< Offset 0x30C Current ALS Luminance Reading
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UINT32 BCLP; ///< Offset 0x310 Requested Backlight Brightness
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UINT32 PFIT; ///< Offset 0x314 Panel Fitting State or Request
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UINT32 CBLV; ///< Offset 0x318 Current Brightness Level
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UINT16 BCLM[0x14]; ///< Offset 0x31C Backlight Brightness Levels Duty Cycle Mapping Table
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UINT8 RSVD[0x82]; ///< Offset 0x344 - 0x3C5 BIOS does not uses this section of OpRegion
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UINT8 VRSR; ///< Offset 0x3C6 VRAM SR supported by driver.
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UINT8 RM32[0x39]; ///< Offset 0x3C7 - 0x3FF Reserved Must be zero.
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} DG_OPREGION_MBOX3;
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///
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/// OpRegion Mailbox 4 - VBT Video BIOS Table
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/// Offset 0x400, Size 0x1800
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///
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typedef struct {
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UINT8 RVBT[0x1800]; ///< Offset 0x400 - 0x1BFF Raw VBT Data
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} DG_OPREGION_MBOX4;
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///
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/// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync
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/// Offset 0x1C00, Size 0x400
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///
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typedef struct {
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UINT8 RSVD[0x400]; ///< Offset 0x1C00 - 0x1FFF BIOS does not uses this section of OPRegion
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} DG_OPREGION_MBOX5;
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///
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/// DG OpRegion Structure
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///
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typedef struct {
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DG_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)
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DG_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100)
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DG_OPREGION_MBOX2 Mbox2; ///< Mailbox 2: Obselete in DG
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DG_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)
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DG_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)
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DG_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)
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} DG_OPREGION_STRUCTURE;
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#pragma pack()
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///
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/// DG OpRegion Protocol
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///
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typedef struct {
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DG_OPREGION_STRUCTURE *OpRegion; ///< DG Operation Region Structure
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} DG_OPREGION_PROTOCOL;
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#define R_SA_DG_ASLS_OFFSET 0x00FC ///< ASL Storage
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///
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/// Native Device Id for DG card in motherboard down configuration
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///
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#define DG2_DEVICE_ID_1 0x5690
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#define DG2_DEVICE_ID_2 0x5691
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#define DG2_DEVICE_ID_3 0x5692
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#define DG2_DEVICE_ID_4 0x5693
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#define DG2_DEVICE_ID_5 0x5694
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#define DG2_DEVICE_ID_6 0x5695
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#define DG2_DEVICE_ID_7 0x5696
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#define DG2_DEVICE_ID_8 0x5697
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#define DG2_DEVICE_ID_9 0x5698
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//[-start-210831-IB05660175-add]//
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#define DG2_DEVICE_ID_10 0x4F81
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//[-end-210831-IB05660175-add]//
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#endif
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