94 lines
4.5 KiB
C
94 lines
4.5 KiB
C
/** @file
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Header file for Tx/Rx ring configuration of USB4 host interface.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _USB4_HI_RING_H_
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#define _USB4_HI_RING_H_
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#define USB4_TX_RING_FULL(prod, cons, size) ((((prod) + 1) % (size)) == (cons))
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#define USB4_TX_RING_EMPTY(prod, cons) ((prod) == (cons))
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#define USB4_RX_RING_FULL(prod, cons) ((prod) == (cons))
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#define USB4_RX_RING_EMPTY(prod, cons, size) ((((cons) + 1) % (size)) == (prod))
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#define USB4_TX_RING_POLL_US 10
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#define USB4_TX_RING_TOTAL_WAITS 200
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#define USB4_RX_RING_POLL_US 50 // 50 us
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#define USB4_RX_RING_TOTAL_WAIT_US 10000000 // 10s
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#define USB4_RX_RING_TOTAL_WAITS (USB4_RX_RING_TOTAL_WAIT_US / USB4_RX_RING_POLL_US)
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#define MAX_PACKETS_TO_RX_WHILE_WAIT_FOR_RESP 1000
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//
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// Register definition of Host Interface Programming interface
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//
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#define REG_TX_RING_BASE 0x00000
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#define REG_RX_RING_BASE 0x08000
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#define REG_RING_PHYS_LO_OFFSET 0
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#define REG_RING_PHYS_HI_OFFSET 4
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#define REG_RING_CONS_PROD_OFFSET 8
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#define REG_RING_CONS_SHIFT 0
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#define REG_RING_CONS_MASK 0x0000FFFF // Bit[15:0]
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#define REG_RING_PROD_SHIFT 16
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#define REG_RING_PROD_MASK 0xFFFF0000 // Bit[31:16]
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#define REG_RING_SIZE_OFFSET 12
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#define REG_RING_SIZE_SHIFT 0
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#define REG_RING_SIZE_MASK 0x0000FFFF // Bit[15:0]
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#define REG_RING_BUF_SIZE_SHIFT 16
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#define REG_RING_BUF_SIZE_MASK 0x0FFF0000 // Bit[27:16]
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#define REG_TX_OPTIONS_BASE 0x19800
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#define REG_RX_OPTIONS_BASE 0x29800
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#define REG_RX_OPTS_MASK_OFFSET 4
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#define REG_RX_OPTS_MASK_EOF_SHIFT 0
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#define REG_RX_OPTS_MASK_EOF_MASK 0x0000FFFF // Bit[15:0]
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#define REG_RX_OPTS_MASK_SOF_SHIFT 16
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#define REG_RX_OPTS_MASK_SOF_MASK 0xFFFF0000 // Bit[31:16]
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#define REG_OPTS_RAW BIT30
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#define REG_OPTS_VALID BIT31
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#define DESC_ATTR_LEN_SHIFT 0
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#define DESC_ATTR_LEN_MASK 0x00000FFF // Bit[11:0]
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#define DESC_ATTR_EOF_SHIFT 12
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#define DESC_ATTR_EOF_MASK 0x0000F000 // Bit[15:12]
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#define DESC_ATTR_SOF_SHIFT 16
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#define DESC_ATTR_SOF_MASK 0x000F0000 // Bit[19:16]
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#define DESC_ATTR_TX_ISOCH_DMA_EN BIT20 // TX
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#define DESC_ATTR_RX_CRC_ERR BIT20 // RX after use
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#define DESC_ATTR_DESC_DONE BIT21
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#define DESC_ATTR_REQ_STS BIT22 // TX and RX before use
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#define DESC_ATTR_RX_BUF_OVRN_ERR BIT22 // RX after use
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#define DESC_ATTR_INT_EN BIT23
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#define DESC_ATTR_OFFSET_SHIFT 24
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#define DESC_ATTR_OFFSET_MASK 0xFF000000 // Bit[31:24]
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#endif
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