205 lines
8.3 KiB
C
205 lines
8.3 KiB
C
/** @file
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PSS(Processor Secured Storage) Chip Operation Library Header
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2017 - 2019 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef __PSS_LIB_H__
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#define __PSS_LIB_H__
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//
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// Monza X-8K PSS Chip Memory Map
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//
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#define MONZAX_SIZE_RESERVED 22
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#define MONZAX_SIZE_EPC 18
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#define MONZAX_SIZE_TID 24
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#define MONZAX_SIZE_USER 1024
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#define PSS_BASE_ADDR_RESERVED 0x00
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#define PSS_BASE_ADDR_EPC 0x16
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#define PSS_BASE_ADDR_TID 0x28
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#define PSS_BASE_ADDR_CLASSID 0x28
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#define PSS_BASE_ADDR_USER 0x40
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#define PSS_BASE_ADDR_MAX 0x43F // 0 ~ 0x43F
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#define PSS_CHIP_TID_LENGTH 12
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#define PSS_SN_LENGTH 16
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//
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// Intel PSS Chip Memory Layout Definition - Start
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// Base address is BASE_ADDRESS_USER(0x40)
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//
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#define PSS_CHIP_BLOCK_0_START (0)
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#define PSS_CHIP_BLOCK_1_START (PSS_CHIP_BLOCK_0_START + 64) // 0x40
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#define PSS_CHIP_BLOCK_2_START (PSS_CHIP_BLOCK_1_START + 64) // 0x80
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#define PSS_CHIP_BLOCK_3_START (PSS_CHIP_BLOCK_2_START + 64) // 0xC0
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#define PSS_CHIP_BLOCK_4_START (PSS_CHIP_BLOCK_3_START + 64) // 0x100
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#define PSS_CHIP_REWORK_OFFSET (PSS_CHIP_BLOCK_0_START) // 0x00
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#define PSS_CHIP_REWORK_LENGTH (12) // Bytes
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#define PSS_CHIP_STATUS_OFFSET (PSS_CHIP_REWORK_OFFSET + PSS_CHIP_REWORK_LENGTH) // 0x0C
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#define PSS_CHIP_STATUS_LENGTH (12)
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#define PSS_CHIP_LAST_PSS_UPDATE_OFFSET (PSS_CHIP_STATUS_OFFSET + PSS_CHIP_STATUS_LENGTH) // 0x18
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#define PSS_CHIP_LAST_PSS_UPDATE_LENGTH (10)
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#define PSS_CHIP_PMIC_VERSION_OFFSET (PSS_CHIP_LAST_PSS_UPDATE_OFFSET + PSS_CHIP_LAST_PSS_UPDATE_LENGTH) // 0x22
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#define PSS_CHIP_PMIC_VERSION_LENGTH (6)
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#define PSS_CHIP_ASSIGNED_USER_OFFSET (PSS_CHIP_PMIC_VERSION_OFFSET + PSS_CHIP_PMIC_VERSION_LENGTH) // 0x28
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#define PSS_CHIP_ASSIGNED_USER_LENGTH (8)
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#define PSS_CHIP_LOCATION_OFFSET (PSS_CHIP_ASSIGNED_USER_OFFSET + PSS_CHIP_ASSIGNED_USER_LENGTH) // 0x30
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#define PSS_CHIP_LOCATION_LENGTH (16)
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#define PSS_CHIP_BOARD_SERIAL_NUMBER_OFFSET (PSS_CHIP_BLOCK_1_START) // 0x40
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#define PSS_CHIP_BOARD_SERIAL_NUMBER_LENGTH (16)
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#define PSS_CHIP_WORK_ORDER_NUMBER_OFFSET (PSS_CHIP_BOARD_SERIAL_NUMBER_OFFSET + PSS_CHIP_BOARD_SERIAL_NUMBER_LENGTH) // 0x50
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#define PSS_CHIP_WORK_ORDER_NUMBER_LENGTH (16)
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#define PSS_CHIP_INTEL_PART_NUMBER_OFFSET (PSS_CHIP_WORK_ORDER_NUMBER_OFFSET + PSS_CHIP_WORK_ORDER_NUMBER_LENGTH) // 0x60
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#define PSS_CHIP_INTEL_PART_NUMBER_LENGTH (12)
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#define PSS_CHIP_PRODUCT_FAMILY_OFFSET (PSS_CHIP_INTEL_PART_NUMBER_OFFSET + PSS_CHIP_INTEL_PART_NUMBER_LENGTH) // 0x6C
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#define PSS_CHIP_PRODUCT_FAMILY_LENGTH (20)
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#define PSS_CHIP_LAST_RFID_SYNC_OFFSET (PSS_CHIP_BLOCK_2_START) // 0x80
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#define PSS_CHIP_LAST_RFID_SYNC_LENGTH (10)
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#define PSS_CHIP_DATE_SHIPPED_OFFSET (PSS_CHIP_LAST_RFID_SYNC_OFFSET + PSS_CHIP_LAST_RFID_SYNC_LENGTH) // 0x8A
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#define PSS_CHIP_DATE_SHIPPED_LENGTH (10)
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#define PSS_CHIP_SPECIAL_INSTRUCTIONS_OFFSET (PSS_CHIP_DATE_SHIPPED_OFFSET + PSS_CHIP_DATE_SHIPPED_LENGTH) // 0x94
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#define PSS_CHIP_SPECIAL_INSTRUCTIONS_LENGTH (32)
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#define PSS_CHIP_RECALL_OFFSET (PSS_CHIP_SPECIAL_INSTRUCTIONS_OFFSET + PSS_CHIP_SPECIAL_INSTRUCTIONS_LENGTH) // 0xB4
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#define PSS_CHIP_RECALL_LENGTH (1)
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#define PSS_CHIP_CONSUMPTION_METER_OFFSET (PSS_CHIP_RECALL_OFFSET + PSS_CHIP_RECALL_LENGTH) // 0xB5
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#define PSS_CHIP_CONSUMPTION_METER_LENGTH (7)
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#define PSS_CHIP_BOOT_COUNT_OFFSET (PSS_CHIP_CONSUMPTION_METER_OFFSET + PSS_CHIP_CONSUMPTION_METER_LENGTH) // 0xBC
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#define PSS_CHIP_BOOT_COUNT_LENGTH (4)
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#define PSS_CHIP_SOC_VERSION_OFFSET (PSS_CHIP_BLOCK_3_START) // 0xC0
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#define PSS_CHIP_SOC_VERSION_LENGTH (8)
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#define PSS_CHIP_BKC_VERSION_OFFSET (PSS_CHIP_SOC_VERSION_OFFSET + PSS_CHIP_SOC_VERSION_LENGTH) // 0xC8
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#define PSS_CHIP_BKC_VERSION_LENGTH (16)
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#define PSS_CHIP_OS_OFFSET (PSS_CHIP_BKC_VERSION_OFFSET + PSS_CHIP_BKC_VERSION_LENGTH) // 0xD8
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#define PSS_CHIP_OS_LENGTH (16)
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#define PSS_CHIP_IFWI_OFFSET (PSS_CHIP_OS_OFFSET + PSS_CHIP_OS_LENGTH) // 0xE8
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#define PSS_CHIP_IFWI_LENGTH (24)
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#define PSS_CHIP_LATITUDE_OFFSET (PSS_CHIP_BLOCK_4_START) // 0x100
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#define PSS_CHIP_LATITUDE_LENGTH (8)
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#define PSS_CHIP_LONGITUDE_OFFSET (PSS_CHIP_LATITUDE_OFFSET + PSS_CHIP_LATITUDE_LENGTH) // 0x108
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#define PSS_CHIP_LONGITUDE_LENGTH (8)
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#define PSS_CHIP_CLASS_ID 0xE2 // TID Offset 0 CLASS_ID[7:0] = 11100010b
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#define PSS_CHIP_TID_DESIGNER_LOW 0x01 // TID Offset 2 Bit 4-7 TID_DESIGNER [3:0] = 0000b
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#define PSS_CHIP_TID_MODEL_HIGH 0x01 // TID Offset 2 Bit 0-3 TID_MODEL [11:8] = 0001b
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#define PSS_CHIP_TID_MODEL_LOW 0x50 // TID Offset 3 Bit 0-7 TID_MODEL [7:0] = 01010000b
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//
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// Intel PSS Chip Memory Layout Definition - End
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//
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#define IsLeap(y) (((y) % 4) == 0 && (((y) % 100) != 0 || ((y) % 400) == 0))
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#define SECSPERMIN (60)
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#define SECSPERHOUR (60 * 60)
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#define SECSPERDAY (24 * SECSPERHOUR)
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#pragma pack (1)
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typedef struct _PSS_CHIP_STRING
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{
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UINT16 Offset;
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UINT8 Length;
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EFI_STRING_ID StringToken;
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}PSS_CHIP_STRING;
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#pragma pack ()
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extern UINTN CumulativeDays[2][14];
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extern CHAR8 *WeekDayName[];
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extern CHAR8 *MonthName[];
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/**
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Read data from PSS chip.
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@param[out] Buffer
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@param[in] Address
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@param[in] Size
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@retval EFI_STATUS
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**/
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EFI_STATUS
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EFIAPI
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ReadPssData (
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UINT8 *Buffer,
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UINT32 Address,
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UINT32 Size
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);
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/**
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Write data to PSS chip.
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@param[in] Buffer
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@param[in] Address
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@param[in] Size
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@retval EFI_STATUS
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**/
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EFI_STATUS
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EFIAPI
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WritePssData (
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UINT8 *Buffer,
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UINT32 Address,
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UINTN Size
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);
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/**
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Check PSS chip status.
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@param[in] none
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@retval EFI_STATUS
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**/
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EFI_STATUS
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EFIAPI
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PssDetect (
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VOID
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);
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/**
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Get 16 bytes Serial Number from PSS chip.
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@param[in] Buffer
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@param[in] Size
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@retval EFI_STATUS
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**/
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EFI_STATUS
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EFIAPI
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PssGetSerialNumber (
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UINT8 *Buffer,
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UINT32 Size
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);
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#endif
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