127 lines
5.2 KiB
C
127 lines
5.2 KiB
C
/** @file
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2016 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PLATFORM_DEFINITIONS_CLOCK_H_
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#define _PLATFORM_DEFINITIONS_CLOCK_H_
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//
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// Clock controller SMBUS address
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//
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#define CLOCK_CONTROLLER_SMBUS_ADDRESS 0xD2
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//
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// Redfort platform CK505 configuration bytes 0~12
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// (Reference: Table 21, CK505 Clock Synthesizer Specification Revision 1.0
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// October 2006 Intel)
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//
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// BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
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// =================================================================================
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// Byte 0
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// ------
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// FSC(r) FSB(r) FSA(r) MT_EN Reserved SRC_MAIN SATA_SEL PD_RESTORE
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// _SEL
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// 0 0 0 0 0 1 0 1
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//
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// Byte 1
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// ------
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// SRC0_SEL PLL1_SSC PLL3_SSC PLL3_CFB3 PLL3_CFB2 PLL3_CFB1 PLL3_CFB0 PCI_SEL
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// _DC _DC
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// 1 0 0 0 0 0 1 1
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//
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// Byte 2
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// ------
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// REF_OE USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE
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// 1 0 0 0 0 0 0 0
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//
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// Byte 3
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// ------
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// SRC11_OE SRC10_OE SRC9_OE SRC8/ITP SRC7_OE SRC6_OE SRC5_OE SRC4_OE
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// _OE
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// 0 0 0 0 0 0 0 0
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//
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// Byte 4
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// ------
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// SRC3_OE SATA/SRC2 SRC1_OE SRC0 CPU1_OE CPU0_OE PLL1_SSC PLL3_SSC_EN
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// _OE /DOT96_OE _EN
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// 0 1 1 1 0 1 0 0
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//
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// Byte 5
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// ------
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// CR#_A_EN CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL
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// 0 0 0 0 0 0 0 0
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//
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// Byte 6
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// ------
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// CR#_E_EN CR#_F_EN CR#_G_EN CR#_H_EN Reserved Reserved SSCD_STP SRC_STP_CRTL
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// _CRTL
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// 0 0 0 0 0 0 0 0
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//
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// Byte 7
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// ------
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// RC Bit3(r) RC Bit2(r) RC Bit1(r) RC Bit0(r) VID Bit3(r)VID Bit2(r)VID Bit1(r)VID Bit0(r)
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// 0 0 0 0 0 0 0 0
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//
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// Byte 8
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// ------
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// DID3(r) DID2(r) DID1(r) DID0(r) Reserved Reserved SE1_OE SE2_OE
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// 0 0 0 0 0 0 0 0
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//
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// Byte 9
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// ------
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// PCIF5_STP TME_STRAP REF_DRIVE TEST_MODE TEST_MODE IO_VOUT2 IO_VOUT1 IO_VOUT0
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// _CTRL (r) _SEL _ENTRY
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// 0 0 1 0 0 1 0 1
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//
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// Byte 10
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// -------
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// SRC5_EN PLL3_EN PLL2_EN SRC_DIV_EN PCI_DIV_EN CPU_DIV_EN CPU1_STOP CPU0_STOP
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// _STRAP(r) _EN _EN
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// 1 1 1 0 0 0 0 0
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//
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// Byte 11
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// -------
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// PCI3_CFG1 PCI3_CFG0 25MHZ_EN PLL4_EN CPU2_AMT CPU1_AMT PCI-E_GEN2 CPU2_STOP
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// (r) (r) _SE1 _EN _EN (r) _EN
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// 0 1 0 1 0 0 1 0
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//
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// Byte 12
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// -------
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// Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0
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// 0 0 0 0 1 1 0 1
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//
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#define MOBILE_CLOCK_CONTROLLER_SETTINGS {0x05, 0x83, 0x80, 0, 0x77, 0x00, 0x0, 0x00, 0, 0x25, 0xe0, 0x52, 0xd}
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#define DESKTOP_CLOCK_CONTROLLER_SETTINGS {0x35, 0x83, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x26, 0x03, 0x25, 0xFD, 0x56}
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#endif
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