316 lines
12 KiB
C
316 lines
12 KiB
C
/** @file
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This file is SampleCode of the library for Intel PCH PEI Debug Policy initialization.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2014 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include <Uefi.h>
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#include <PiPei.h>
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#include <SetupVariable.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Ppi/ReadOnlyVariable2.h>
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#include <Library/PeiServicesLib.h>
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#include <Ppi/SiPolicy.h>
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#include <Library/PchInfoLib.h>
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#include <Library/SiPolicyLib.h>
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#if FixedPcdGet8(PcdFspModeSelection) == 1
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#include <FspsUpd.h>
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#endif
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#include <PolicyUpdateMacro.h>
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/**
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Update PCIE Root Port debug policies
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@param[in] SiPolicy Pointer to SI_POLICY_PPI
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@param[in] FspsUpd Pointer to FSPS_UPD
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@param[in] PchSetup Pointer to PCH_SETUP buffer
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**/
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STATIC
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VOID
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UpdatePcieRpDebugPolicy (
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IN SI_POLICY_PPI *SiPolicy,
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IN VOID *FspsUpd,
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IN PCH_SETUP *PchSetup
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)
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{
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UINT8 Index;
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#if FixedPcdGet8(PcdFspModeSelection) == 0
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EFI_STATUS Status;
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PCH_PCIE_CONFIG *PchPcieConfig;
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Status = GetConfigBlock ((VOID *) SiPolicy, &gPchPcieConfigGuid, (VOID *) &PchPcieConfig);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return;
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}
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#endif
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieEnablePort8xhDecode, PchPcieConfig->PcieCommonConfig.EnablePort8xhDecode, PchSetup->PcieRootPort8xhDecode);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchPciePort8xhDecodePortIndex, PchPcieConfig->PchPciePort8xhDecodePortIndex, PchSetup->Pcie8xhDecodePortIndex);
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for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
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if (PchSetup->PchPcieLtrEnable[Index]) {
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpLtrMaxSnoopLatency[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxSnoopLatency, 0x1003);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpLtrMaxNoSnoopLatency[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxNoSnoopLatency, 0x1003);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpSnoopLatencyOverrideMode[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.SnoopLatencyOverrideMode, PchSetup->PchPcieSnoopLatencyOverrideMode[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpSnoopLatencyOverrideMultiplier[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.SnoopLatencyOverrideMultiplier, PchSetup->PchPcieSnoopLatencyOverrideMultiplier[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpNonSnoopLatencyOverrideMode[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.NonSnoopLatencyOverrideMode, PchSetup->PchPcieNonSnoopLatencyOverrideMode[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.NonSnoopLatencyOverrideMultiplier, PchSetup->PchPcieNonSnoopLatencyOverrideMultiplier[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpSnoopLatencyOverrideValue[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.SnoopLatencyOverrideValue, PchSetup->PchPcieSnoopLatencyOverrideValue[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpNonSnoopLatencyOverrideValue[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.NonSnoopLatencyOverrideValue, PchSetup->PchPcieNonSnoopLatencyOverrideValue[Index]);
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}
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}
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}
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/**
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Update PCH DMI debug policies.
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@param[in] SiPolicy Pointer to SI_POLICY_PPI
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@param[in] FspsUpd Pointer to FspsUpd structure
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@param[in] PchSetup Pointer to PCH_SETUP buffer
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**/
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STATIC
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VOID
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UpdatePchDmiDebugPolicy (
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IN SI_POLICY_PPI *SiPolicy,
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IN VOID *FspsUpd,
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IN PCH_SETUP *PchSetup
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)
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{
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UINT8 Index;
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#if FixedPcdGet8(PcdFspModeSelection) == 0
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EFI_STATUS Status;
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PCH_DMI_CONFIG *PchDmiConfig;
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Status = GetConfigBlock ((VOID *) SiPolicy, &gPchDmiConfigGuid, (VOID *) &PchDmiConfig);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return;
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}
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#endif
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for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
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if (PchSetup->PchPcieLtrEnable[Index] == TRUE) {
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchPwrOptEnable, PchDmiConfig->PwrOptEnable, TRUE);
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return;
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}
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}
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}
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/**
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Update SATA debug policies.
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@param[in] SiPolicy Pointer to SI_POLICY_PPI
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@param[in] FspsUpd Pointer to FspsUpd structure
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@param[in] PchSetup Pointer to PCH_SETUP buffer
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**/
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STATIC
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VOID
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UpdateSataDebugPolicy (
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IN SI_POLICY_PPI *SiPolicy,
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IN VOID *FspsUpd,
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IN PCH_SETUP *PchSetup
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)
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{
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#if FixedPcdGet8(PcdFspModeSelection) == 0
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EFI_STATUS Status;
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SATA_CONFIG *SataConfig;
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Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return;
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}
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#endif
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SataTestMode, SataConfig->TestMode, PchSetup->SataTestMode);
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}
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/**
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Update USB debug policies.
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@param[in] SiPolicy Pointer to SI_POLICY_PPI
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@param[in] FspsUpd Pointer to FspsUpd structure
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@param[in] PchSetup Pointer to PCH_SETUP buffer
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**/
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STATIC
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VOID
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UpdateUsbDebugPolicy (
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IN SI_POLICY_PPI *SiPolicy,
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IN VOID *FspsUpd,
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IN PCH_SETUP *PchSetup
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)
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{
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#if FixedPcdGet8(PcdFspModeSelection) == 0
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EFI_STATUS Status;
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USB_CONFIG *UsbConfig;
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Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return;
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}
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#endif
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchXhciOcLock, UsbConfig->XhciOcLock, PchSetup->PchXhciOcLock);
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}
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/**
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Update Power Management debug policies.
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@param[in] SiPolicy Pointer to SI_POLICY_PPI
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@param[in] FspsUpd Pointer to FspsUpd structure
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@param[in] PchSetup Pointer to PCH_SETUP buffer
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**/
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STATIC
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VOID
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UpdatePmDebugPolicy (
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IN SI_POLICY_PPI *SiPolicy,
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IN VOID *FspsUpd,
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IN PCH_SETUP *PchSetup
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)
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{
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#if FixedPcdGet8(PcdFspModeSelection) == 0
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EFI_STATUS Status;
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PCH_PM_CONFIG *PmConfig;
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Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return;
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}
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#endif
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchPmDisableEnergyReport, PmConfig->DisableEnergyReport, (PchSetup->PchEnergyReport == 1)? 0 : 1);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PmcLpmS0ixSubStateEnableMask, PmConfig->LpmS0ixSubStateEnable.Val, ((PchSetup->PmcLpmS0i2p0En << 0) |
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(PchSetup->PmcLpmS0i2p1En << 1) |
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(PchSetup->PmcLpmS0i2p2En << 2) |
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(PchSetup->PmcLpmS0i3p0En << 3) |
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(PchSetup->PmcLpmS0i3p1En << 4) |
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(PchSetup->PmcLpmS0i3p2En << 5) |
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(PchSetup->PmcLpmS0i3p3En << 6) |
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(PchSetup->PmcLpmS0i3p4En << 7)));
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}
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/**
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Update P2sb debug policies.
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@param[in] SiPolicy Pointer to SI_POLICY_PPI
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@param[in] FspsUpd Pointer to FspsUpd structure
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@param[in] PchSetup Pointer to PCH_SETUP buffer
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**/
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STATIC
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VOID
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UpdateP2sbDebugPolicy (
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IN SI_POLICY_PPI *SiPolicy,
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IN VOID *FspsUpd,
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IN PCH_SETUP *PchSetup
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)
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{
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#if FixedPcdGet8(PcdFspModeSelection) == 0
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EFI_STATUS Status;
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PCH_P2SB_CONFIG *P2sbConfig;
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Status = GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID *) &P2sbConfig);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return;
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}
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#endif
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchSbAccessUnlock, P2sbConfig->SbAccessUnlock, PchSetup->PchSidebandLock ? 0 : 1);
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}
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/**
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This function performs PCH PEI Debug Policy initialization.
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@retval EFI_SUCCESS The PPI is installed and initialized.
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@retval EFI ERRORS The PPI is not successfully installed.
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**/
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EFI_STATUS
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EFIAPI
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UpdatePeiPchPolicyDebug (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
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UINTN VariableSize;
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PCH_SETUP PchSetup;
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SI_POLICY_PPI *SiPolicy;
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VOID *FspsUpd;
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DEBUG ((DEBUG_INFO, "Update PeiPchPolicyDebug Pos-Mem Start\n"));
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#if FixedPcdGet8(PcdFspModeSelection) == 1
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FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
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ASSERT (FspsUpd != NULL);
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SiPolicy = NULL;
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#else
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Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicy);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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FspsUpd = NULL;
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#endif
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//
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// Retrieve Setup variable
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//
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Status = PeiServicesLocatePpi (
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&gEfiPeiReadOnlyVariable2PpiGuid, // GUID
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0, // INSTANCE
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NULL, // EFI_PEI_PPI_DESCRIPTOR
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(VOID **) &VariableServices // PPI
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);
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ASSERT_EFI_ERROR (Status);
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VariableSize = sizeof (PCH_SETUP);
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Status = VariableServices->GetVariable (
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VariableServices,
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L"PchSetup",
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&gPchSetupVariableGuid,
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NULL,
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&VariableSize,
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&PchSetup
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);
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ASSERT_EFI_ERROR (Status);
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UpdatePcieRpDebugPolicy (SiPolicy, FspsUpd, &PchSetup);
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UpdatePchDmiDebugPolicy (SiPolicy, FspsUpd, &PchSetup);
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UpdateSataDebugPolicy (SiPolicy, FspsUpd, &PchSetup);
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UpdateUsbDebugPolicy (SiPolicy, FspsUpd, &PchSetup);
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UpdatePmDebugPolicy (SiPolicy, FspsUpd, &PchSetup);
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UpdateP2sbDebugPolicy (SiPolicy, FspsUpd, &PchSetup);
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return Status;
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}
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