253 lines
11 KiB
C
253 lines
11 KiB
C
/** @file
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This file is SampleCode of the library for Intel SA PEI Debug Policy initialization.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2014 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include "PeiPolicyDebug.h"
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#include <Library/PeiSaPolicyLib.h>
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#include <CpuRegs.h>
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#include <Library/CpuPlatformLib.h>
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#include <Guid/AcpiVariable.h>
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#include <Guid/MemoryTypeInformation.h>
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#include <Library/HobLib.h>
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#include <Platform.h>
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#include <Library/PchInfoLib.h>
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#include <PolicyUpdateMacro.h>
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#include <CpuDmiPreMemConfig.h>
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/**
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This function performs SA PEI Debug PreMem Policy initialization.
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@retval EFI_SUCCESS The PPI is installed and initialized.
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@retval EFI ERRORS The PPI is not successfully installed.
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**/
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EFI_STATUS
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EFIAPI
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UpdatePeiSaPolicyDebugPreMem (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
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SA_SETUP SaSetup;
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UINTN VarSize;
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#if FixedPcdGet8(PcdFspModeSelection) == 1
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VOID *FspmUpd;
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#else
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SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
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GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig;
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PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig;
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SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
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CPU_DMI_PREMEM_CONFIG *CpuDmiPreMemConfig;
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#endif
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DEBUG ((DEBUG_INFO, "Update PeiSaPolicyDebug Pre-Mem Start\n"));
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#if FixedPcdGet8(PcdFspModeSelection) == 1
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FspmUpd = NULL;
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#else
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SiPreMemPolicyPpi = NULL;
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GtPreMemConfig = NULL;
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PciePeiPreMemConfig = NULL;
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MiscPeiPreMemConfig = NULL;
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#endif
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#if FixedPcdGet8(PcdFspModeSelection) == 1
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FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
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ASSERT (FspmUpd != NULL);
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#else
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Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPreMemConfigGuid, (VOID *) &GtPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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#if FixedPcdGetBool(PcdCpuPcieEnable) == 1
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuPciePeiPreMemConfigGuid, (VOID *) &PciePeiPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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#endif
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuDmiPreMemConfigGuid, (VOID *) &CpuDmiPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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#endif
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//
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// Locate system configuration variable
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//
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Status = PeiServicesLocatePpi (
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&gEfiPeiReadOnlyVariable2PpiGuid, // GUID
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0, // INSTANCE
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NULL, // EFI_PEI_PPI_DESCRIPTOR
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(VOID **) &VariableServices // PPI
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);
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ASSERT_EFI_ERROR ( Status);
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//
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// Get Setup SA variables
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//
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VarSize = sizeof (SA_SETUP);
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Status = VariableServices->GetVariable (
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VariableServices,
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L"SaSetup",
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&gSaSetupVariableGuid,
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NULL,
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&VarSize,
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&SaSetup
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);
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if (!EFI_ERROR (Status)) {
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///
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/// Initialize the DMI Configuration
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///
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UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DmiMaxLinkSpeed, CpuDmiPreMemConfig->DmiMaxLinkSpeed, SaSetup.DmiMaxLinkSpeed);
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UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DmiGen3EqPh2Enable, CpuDmiPreMemConfig->DmiGen3EqPh2Enable, SaSetup.DmiGen3EqPh2Enable);
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UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DmiGen3EqPh3Method, CpuDmiPreMemConfig->DmiGen3EqPh3Method, SaSetup.DmiGen3EqPh3Method);
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//
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// Initialize the Graphics configuration
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//
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UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PanelPowerEnable, GtPreMemConfig->PanelPowerEnable, SaSetup.PanelPowerEnable);
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//
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// Disable PanelPowerEnable if there is no eDP present on DDI-A & B.
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//
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#if FixedPcdGet8(PcdFspModeSelection) == 1
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if ((((FSPM_UPD *)FspmUpd)->FspmConfig.DdiPortAConfig != DdiPortEdp) && (((FSPM_UPD *)FspmUpd)->FspmConfig.DdiPortBConfig != DdiPortEdp)) {
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#else
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if ((GtPreMemConfig->DdiConfiguration.DdiPortAConfig != DdiPortEdp) && (GtPreMemConfig->DdiConfiguration.DdiPortBConfig != DdiPortEdp)) {
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#endif
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UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PanelPowerEnable, GtPreMemConfig->PanelPowerEnable, 0x0);
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}
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//
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// Initialize Misc SA Configuration
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//
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UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.LockPTMregs, MiscPeiPreMemConfig->LockPTMregs, SaSetup.LockPTMregs);
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UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BdatEnable, MiscPeiPreMemConfig->BdatEnable, SaSetup.BdatEnable);
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UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BdatTestType, MiscPeiPreMemConfig->BdatTestType, SaSetup.BdatTestType);
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}
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return Status;
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}
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/**
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This function performs SA PEI Debug Policy initialization.
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@retval EFI_SUCCESS The PPI is installed and initialized.
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@retval EFI ERRORS The PPI is not successfully installed.
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**/
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EFI_STATUS
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EFIAPI
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UpdatePeiSaPolicyDebug(
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VOID
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)
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{
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EFI_STATUS Status;
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#if FixedPcdGetBool(PcdCpuPcieEnable) == 1
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UINT8 Index;
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#endif
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
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UINTN VariableSize;
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SA_SETUP SaSetup;
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#if FixedPcdGet8(PcdFspModeSelection) == 1
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VOID *FspsUpd;
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#else
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SI_POLICY_PPI *SiPolicyPpi;
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CPU_PCIE_CONFIG *CpuPcieRpConfig;
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#endif
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DEBUG ((DEBUG_INFO, "Update PeiSaPolicyDebug Post-Mem Start\n"));
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#if FixedPcdGet8(PcdFspModeSelection) == 1
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FspsUpd = NULL;
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#else
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SiPolicyPpi = NULL;
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CpuPcieRpConfig = NULL;
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#endif
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#if FixedPcdGet8(PcdFspModeSelection) == 1
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FspsUpd = (FSPS_UPD *)PcdGet32(PcdFspsUpdDataAddress);
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ASSERT(FspsUpd != NULL);
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#else
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Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
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ASSERT_EFI_ERROR(Status);
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#if FixedPcdGetBool(PcdCpuPcieEnable) == 1
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Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPcieRpConfigGuid, (VOID *) &CpuPcieRpConfig);
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ASSERT_EFI_ERROR(Status);
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#endif
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#endif
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//
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// Retrieve Setup variable
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//
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Status = PeiServicesLocatePpi (
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&gEfiPeiReadOnlyVariable2PpiGuid, // GUID
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0, // INSTANCE
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NULL, // EFI_PEI_PPI_DESCRIPTOR
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(VOID **) &VariableServices // PPI
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);
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ASSERT_EFI_ERROR (Status);
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VariableSize = sizeof (SA_SETUP);
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Status = VariableServices->GetVariable (
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VariableServices,
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L"SaSetup",
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&gSaSetupVariableGuid,
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NULL,
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&VariableSize,
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&SaSetup
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);
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ASSERT_EFI_ERROR (Status);
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#if FixedPcdGetBool(PcdCpuPcieEnable) == 1
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for (Index = 0; Index < GetMaxCpuPciePortNum (); Index++) {
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpLtrMaxSnoopLatency[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxSnoopLatency, 0x100F);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpLtrMaxNoSnoopLatency[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxNoSnoopLatency, 0x100F);
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if (SaSetup.CpuPcieLtrEnable[Index] == TRUE) {
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpLtrMaxSnoopLatency[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxSnoopLatency, 0x100F);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpLtrMaxNoSnoopLatency[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxNoSnoopLatency, 0x100F);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpSnoopLatencyOverrideMode[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.SnoopLatencyOverrideMode, SaSetup.CpuPcieSnoopLatencyOverrideMode[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpSnoopLatencyOverrideMultiplier[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.SnoopLatencyOverrideMultiplier, SaSetup.CpuPcieSnoopLatencyOverrideMultiplier[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpNonSnoopLatencyOverrideMode[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.NonSnoopLatencyOverrideMode, SaSetup.CpuPcieNonSnoopLatencyOverrideMode[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpNonSnoopLatencyOverrideMultiplier[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.NonSnoopLatencyOverrideMultiplier, SaSetup.CpuPcieNonSnoopLatencyOverrideMultiplier[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpSnoopLatencyOverrideValue[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.SnoopLatencyOverrideValue, SaSetup.CpuPcieSnoopLatencyOverrideValue[Index]);
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UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.CpuPcieRpNonSnoopLatencyOverrideValue[Index], CpuPcieRpConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.NonSnoopLatencyOverrideValue, SaSetup.CpuPcieNonSnoopLatencyOverrideValue[Index]);
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}
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}
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#endif
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return Status;
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}
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