908 lines
35 KiB
C
908 lines
35 KiB
C
/** @file
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Pci Hotplug Driver : This file will perform specific PCI-EXPRESS
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Devics resource configuration.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2006 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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//
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// Statements that include other files
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//
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#include "PciHotPlug.h"
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#include "PciHotPlugHelpers.h"
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#include <Protocol/ITbtPolicy.h>
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#if FixedPcdGetBool (PcdDTbtEnable) == 1
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#include <Protocol/DxeDTbtPolicy.h>
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#endif
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#include <Library/PchPcieRpLib.h>
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#include <Library/TbtCommonLib.h>
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#include <Register/SaRegsHostBridge.h>
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#include <PchBdfAssignment.h>
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#include <Library/ItbtPcieRpLib.h>
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#include <Library/TcssInfoLib.h>
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#define ITBT_CONTROLLER 0x80
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#define INVALID_RP_CONTROLLER_TYPE 0xFF
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#define PCIE_NUM (24)
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#define PEG_NUM (4)
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#define PADDING_BUS (1)
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#define PADDING_NONPREFETCH_MEM (1)
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#define PADDING_PREFETCH_MEM (1)
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#define PADDING_IO (1)
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#define PADDING_NUM (PADDING_BUS + PADDING_NONPREFETCH_MEM + PADDING_PREFETCH_MEM + PADDING_IO)
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_HPC_LOCATION mPcieLocation[PCIE_NUM + PEG_NUM + MAX_ITBT_PCIE_PORT];
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GLOBAL_REMOVE_IF_UNREFERENCED P2PB_RESOURCE_RECORD mP2pbResourceRecord[MAX_P2PB_OF_TBT_DAISY_CHAIN];
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mP2pbResourceRecordCount = 0;
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// Record the number of HotPlug capability Bridge on the same Bus.
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GLOBAL_REMOVE_IF_UNREFERENCED NUMBER_OF_HOTPLUG_BRIDGE mNumOfHotPlugBridge[MAX_P2PB_OF_TBT_DAISY_CHAIN];
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GLOBAL_REMOVE_IF_UNREFERENCED UINTN mHpcCount = 0;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mRemainderBus = 0;
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GLOBAL_REMOVE_IF_UNREFERENCED UINTN gItbtSegment = 0;
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GLOBAL_REMOVE_IF_UNREFERENCED PCIE_HOT_PLUG_DEVICE_PATH mHotplugPcieDevicePathTemplate = {
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ACPI,
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PCI(0xFF, 0xFF), // Dummy Device no & Function no
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END
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};
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/**
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Entry point for the driver.
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This routine reads the PlatformType GPI on FWH and produces a protocol
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to be consumed by the chipset driver to effect those settings.
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@param[in] ImageHandle An image handle.
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@param[in] SystemTable A pointer to the system table.
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@retval EFI_SUCCESS.
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**/
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EFI_STATUS
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EFIAPI
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PciHotPlug (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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PCI_HOT_PLUG_INSTANCE *PciHotPlug;
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SA_POLICY_PROTOCOL *SaPolicy;
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UINTN Index;
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UINTN RpDev;
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UINTN RpFunc;
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PCIE_HOT_PLUG_DEVICE_PATH *HotplugPcieDevicePath;
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UINTN VariableSize;
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PCH_SETUP PchSetup;
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PCIE_DXE_CONFIG *PcieDxeConfig;
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ITBT_INFO_HOB *ITbtInfoHob;
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UINTN RpBus;
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UINTN RpSegment;
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UINT8 PegDeviceNumber [SA_PEG_MAX_FUN] = {1, 1, 1, 6};
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UINT8 PegFunctionNumber [SA_PEG_MAX_FUN] = {0, 1, 2, 0};
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RpSegment = 0;
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RpDev = 0;
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RpFunc = 0;
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//
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// Get TBT INFO HOB
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//
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ITbtInfoHob = NULL;
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ITbtInfoHob = (ITBT_INFO_HOB *) GetFirstGuidHob (&gITbtInfoHobGuid);
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if (ITbtInfoHob == NULL) {
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DEBUG ((DEBUG_INFO, "PciHotPlug - ITbtInfoHob not found\n"));
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}
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ZeroMem (mP2pbResourceRecord, sizeof (mP2pbResourceRecord));
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ZeroMem (mNumOfHotPlugBridge, sizeof (mNumOfHotPlugBridge));
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VariableSize = sizeof (PCH_SETUP);
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Status = gRT->GetVariable (
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L"PchSetup",
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&gPchSetupVariableGuid,
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NULL,
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&VariableSize,
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&PchSetup
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);
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ASSERT_EFI_ERROR (Status);
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//
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// PCH Rootports Hotplug device path creation
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//
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for (Index = 0; Index < PCIE_NUM; Index++) {
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if (PchSetup.PcieRootPortHPE[Index]) { // Check the Rootport no's hotplug is set
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DEBUG ((DEBUG_INFO, "Index (%02d)\n", Index));
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Status = GetPchPcieRpDevFun (Index, &RpDev, &RpFunc); // Get the actual device/function no corresponding to the Rootport no provided
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ASSERT_EFI_ERROR (Status);
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HotplugPcieDevicePath = NULL;
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HotplugPcieDevicePath = AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
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ASSERT (HotplugPcieDevicePath != NULL);
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if (HotplugPcieDevicePath == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
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HotplugPcieDevicePath->PciRootPortNode.Device = (UINT8) RpDev; // Update real Device no
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HotplugPcieDevicePath->PciRootPortNode.Function = (UINT8) RpFunc; // Update real Function no
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mPcieLocation[mHpcCount].HpcDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
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mPcieLocation[mHpcCount].HpbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
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mHpcCount++;
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DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PCH RP#) : Bus 0x00, Device 0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount, RpDev, RpFunc));
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}
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}
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Status = gBS->LocateProtocol (
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&gSaPolicyProtocolGuid,
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NULL,
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(VOID**) &SaPolicy
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);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *)SaPolicy, &gPcieDxeConfigGuid, (VOID *)&PcieDxeConfig);
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ASSERT_EFI_ERROR (Status);
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//
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// PEG Rootports Hotplug device path creation
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//
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for (Index = 0; Index < (SA_PEG_MAX_FUN); Index++) {
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if (PcieDxeConfig->PegRootPortHPE[Index]) { // Check the Rootport no's hotplug is set
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RpDev = PegDeviceNumber[Index];
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RpFunc = PegFunctionNumber[Index];
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HotplugPcieDevicePath = NULL;
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HotplugPcieDevicePath = AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
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ASSERT (HotplugPcieDevicePath != NULL);
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if (HotplugPcieDevicePath == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
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HotplugPcieDevicePath->PciRootPortNode.Device = (UINT8) RpDev; // Update real Device no
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HotplugPcieDevicePath->PciRootPortNode.Function = (UINT8) RpFunc; // Update real Function no
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mPcieLocation[mHpcCount].HpcDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
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mPcieLocation[mHpcCount].HpbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
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mHpcCount++;
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DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PEG RP#) : Bus 0x00, Device 0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount, RpDev, RpFunc));
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}
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}
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for (Index = 0; Index < MAX_ITBT_PCIE_PORT; Index++) {
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if((ITbtInfoHob != NULL) && (ITbtInfoHob->ITbtRootPortConfig[Index].ITbtPcieRootPortEn)) {
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Status = GetItbtPcieRpInfo((UINTN) Index, &RpSegment, &RpBus, &RpDev, &RpFunc);
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ASSERT_EFI_ERROR (Status);
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gItbtSegment = RpSegment;
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HotplugPcieDevicePath = NULL;
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HotplugPcieDevicePath = AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
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ASSERT (HotplugPcieDevicePath != NULL);
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if (HotplugPcieDevicePath == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
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HotplugPcieDevicePath->PciRootPortNode.Device = (UINT8) RpDev; // Update real Device no
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HotplugPcieDevicePath->PciRootPortNode.Function = (UINT8) RpFunc; // Update real Function no
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mPcieLocation[mHpcCount].HpcDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
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mPcieLocation[mHpcCount].HpbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
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mHpcCount++;
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DEBUG ((DEBUG_INFO, "(%02d) CPU PCIe HotPlug (ITBT RP#) : Bus 0x00, Device 0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount, RpDev, RpFunc));
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}
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}
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PciHotPlug = AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE));
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ASSERT (PciHotPlug != NULL);
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if (PciHotPlug == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// Initialize driver private data.
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//
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ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE));
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PciHotPlug->Signature = PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE;
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PciHotPlug->HotPlugInitProtocol.GetRootHpcList = GetRootHpcList;
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PciHotPlug->HotPlugInitProtocol.InitializeRootHpc = InitializeRootHpc;
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PciHotPlug->HotPlugInitProtocol.GetResourcePadding = GetResourcePadding;
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Status = gBS->InstallProtocolInterface (
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&PciHotPlug->Handle,
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&gEfiPciHotPlugInitProtocolGuid,
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EFI_NATIVE_INTERFACE,
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&PciHotPlug->HotPlugInitProtocol
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);
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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}
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/**
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This procedure returns a list of Root Hot Plug controllers that require
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initialization during boot process
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@param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
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@param[out] HpcCount The number of Root HPCs returned.
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@param[out] HpcList The list of Root HPCs. HpcCount defines the number of elements in this list.
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@retval EFI_SUCCESS.
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**/
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EFI_STATUS
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EFIAPI
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GetRootHpcList (
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IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
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OUT UINTN *HpcCount,
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OUT EFI_HPC_LOCATION **HpcList
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)
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{
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*HpcCount = mHpcCount;
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*HpcList = mPcieLocation;
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return EFI_SUCCESS;
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}
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/**
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This procedure Initializes one Root Hot Plug Controller
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This process may casue initialization of its subordinate buses
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@param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
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@param[in] HpcDevicePath The Device Path to the HPC that is being initialized.
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@param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
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@param[in] Event The event that should be signaled when the Hot Plug Controller initialization is complete. Set to NULL if the caller wants to wait until the entire initialization process is complete. The event must be of the type EFI_EVT_SIGNAL.
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@param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_Hpc_STATE is defined in section 3.1.
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@retval EFI_SUCCESS.
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**/
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EFI_STATUS
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EFIAPI
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InitializeRootHpc (
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IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
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IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
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IN UINT64 HpcPciAddress,
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IN EFI_EVENT Event, OPTIONAL
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OUT EFI_HPC_STATE *HpcState
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)
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{
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if (Event) {
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gBS->SignalEvent (Event);
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}
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*HpcState = EFI_HPC_STATE_INITIALIZED;
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return EFI_SUCCESS;
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}
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/**
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Selects the proper TBT Root port to assign resources
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based on the user input value
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@param[in] SetupData Pointer to Setup data
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@retval TbtSelectorChosen Rootport number.
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**/
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UINT8
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GetRootporttoSetResourcesforTbt (
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IN SETUP_DATA *SetupData,
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IN UINTN RpIndex,
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IN UINT8 TbtType
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)
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{
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UINT8 TbtSelectorChosen;
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UINT8 Index;
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UINT8 Rootportselected;
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#if FixedPcdGetBool (PcdDTbtEnable) == 1
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DTBT_INFO_HOB *DTbtInfoHob;
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#endif
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TbtSelectorChosen = 0xFF;
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Rootportselected = 0;
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#if FixedPcdGetBool (PcdDTbtEnable) == 1
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//
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// Get DTBT INFO HOB
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//
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DTbtInfoHob = NULL;
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Rootportselected = 0;
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DTbtInfoHob = (DTBT_INFO_HOB *) GetFirstGuidHob (&gDTbtInfoHobGuid);
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if ((TbtType == PCIE_RP_TYPE_PCH) || (TbtType == PCIE_RP_TYPE_CPU)) {
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if (DTbtInfoHob == NULL) {
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DEBUG ((DEBUG_INFO, "DTbtInfoHob not found\n"));
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return 0xFF;
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}
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for (Index = 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) {
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if (DTbtInfoHob->DTbtControllerConfig[Index].DTbtControllerEn == 0x01) {
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//
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// Check if Root Index is for PCH PCIe or PEG
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//
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if (DTbtInfoHob->DTbtControllerConfig[Index].Type == TbtType) {
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//
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// Check if Controller is Enabled or not.
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if (SetupData->DTbtController[Index] == 0x01) {
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//
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// Get the Exact Root port number corresponding to the Controller Selected
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//
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Rootportselected = (DTbtInfoHob->DTbtControllerConfig[Index].PcieRpNumber - 1);
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}
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if (Rootportselected == (UINT8) RpIndex) {
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TbtSelectorChosen = Index;
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break;
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}
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} // Type
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}
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} // for loop
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}
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#endif
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if (TbtType == ITBT_CONTROLLER) {
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for (Index = 0; Index < MAX_ITBT_PCIE_PORT; Index++) {
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//
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// Check if Controller is set to AUTO and Enabled by default.
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//
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if (SetupData->ITbtRootPort[Index] == 0x01) {
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//
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// Get the Exact Root port number corresponding to the Controller Selected
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//
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Rootportselected = Index;
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}
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if (Rootportselected == (UINT8) RpIndex) {
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TbtSelectorChosen = Index;
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break;
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}
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} // for loop
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}
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DEBUG ((DEBUG_INFO, "TbtSelectorChosen = %x\n", TbtSelectorChosen));
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return (TbtSelectorChosen);
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}
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/**
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Update P2P Bridge Resource Record
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@param[in] *HpcDevicePath The Device Path to the HPC that is being initialized.
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@param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
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@param[in] RsvdExtraBusNum Reserved Bus resource Number.
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@param[in] RsvdPcieMegaMem Reserved Alignment of MEM resource.
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@param[in] PcieMemAddrRngMax Alignment of MEM resource.
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@param[in] RsvdPciePMegaMem Reserved Pcie Kilo Io Number.
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@param[in] PciePMemAddrRngMax Alignment of PMEM resource.
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@param[in] RsvdPcieKiloIo Reserved Pcie Kilo Io Number.
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@retval EFI_SUCCESS.
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**/
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EFI_STATUS
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UpdateP2pbResourceRecord (
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IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
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IN UINT64 HpcPciAddress,
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IN UINT8 RsvdExtraBusNum,
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IN UINT16 RsvdPcieMegaMem,
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IN UINT8 PcieMemAddrRngMax,
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IN UINT16 RsvdPciePMegaMem,
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IN UINT8 PciePMemAddrRngMax,
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IN UINT8 RsvdPcieKiloIo
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)
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{
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UINT16 Index;
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for (Index = 0; Index < MAX_P2PB_OF_TBT_DAISY_CHAIN; Index++) {
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if (mP2pbResourceRecord[Index].HpcPciAddress == 0) {
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continue;
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}
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if (mP2pbResourceRecord[Index].HpcPciAddress == HpcPciAddress) {
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//
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// Record already existed, so ignore it.
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//
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return EFI_ABORTED;
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}
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}
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//
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// Record the current HPC's resource assignment
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//
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mP2pbResourceRecord[mP2pbResourceRecordCount].HpcDevicePath = HpcDevicePath;
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mP2pbResourceRecord[mP2pbResourceRecordCount].HpcPciAddress = HpcPciAddress;
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mP2pbResourceRecord[mP2pbResourceRecordCount].RsvdExtraBusNum = RsvdExtraBusNum;
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mP2pbResourceRecord[mP2pbResourceRecordCount].RsvdPcieMegaMem = RsvdPcieMegaMem;
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mP2pbResourceRecord[mP2pbResourceRecordCount].PcieMemAddrRngMax = PcieMemAddrRngMax;
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mP2pbResourceRecord[mP2pbResourceRecordCount].RsvdPciePMegaMem = RsvdPciePMegaMem;
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mP2pbResourceRecord[mP2pbResourceRecordCount].PciePMemAddrRngMax = PciePMemAddrRngMax;
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mP2pbResourceRecord[mP2pbResourceRecordCount].RsvdPcieKiloIo = RsvdPcieKiloIo;
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DEBUG ((DEBUG_INFO, "mP2pbResourceRecord[%x].HpcDevicePath = %s \n", mP2pbResourceRecordCount, ConvertDevicePathToText (mP2pbResourceRecord[mP2pbResourceRecordCount].HpcDevicePath, TRUE, TRUE)));
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DEBUG ((DEBUG_INFO, "mP2pbResourceRecord[%x].HpcPciAddress = %lx \n", mP2pbResourceRecordCount, mP2pbResourceRecord[mP2pbResourceRecordCount].HpcPciAddress));
|
|
DEBUG ((DEBUG_INFO, "mP2pbResourceRecord[%x].RsvdExtraBusNum = %x \n", mP2pbResourceRecordCount, mP2pbResourceRecord[mP2pbResourceRecordCount].RsvdExtraBusNum));
|
|
DEBUG ((DEBUG_INFO, "mP2pbResourceRecord[%x].RsvdPcieMegaMem = %x \n", mP2pbResourceRecordCount, mP2pbResourceRecord[mP2pbResourceRecordCount].RsvdPcieMegaMem));
|
|
DEBUG ((DEBUG_INFO, "mP2pbResourceRecord[%x].PcieMemAddrRngMax = %x \n", mP2pbResourceRecordCount, mP2pbResourceRecord[mP2pbResourceRecordCount].PcieMemAddrRngMax));
|
|
DEBUG ((DEBUG_INFO, "mP2pbResourceRecord[%x].RsvdPciePMegaMem = %x \n", mP2pbResourceRecordCount, mP2pbResourceRecord[mP2pbResourceRecordCount].RsvdPciePMegaMem));
|
|
DEBUG ((DEBUG_INFO, "mP2pbResourceRecord[%x].PciePMemAddrRngMax = %x \n", mP2pbResourceRecordCount, mP2pbResourceRecord[mP2pbResourceRecordCount].PciePMemAddrRngMax));
|
|
DEBUG ((DEBUG_INFO, "mP2pbResourceRecord[%x].RsvdPcieKiloIo = %x \n", mP2pbResourceRecordCount, mP2pbResourceRecord[mP2pbResourceRecordCount].RsvdPcieKiloIo));
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Handle the Resource Padding For RootPort
|
|
|
|
@param[in] *HpcDevicePath The Device Path to the HPC that is being initialized.
|
|
@param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
|
|
@param[in] RsvdExtraBusNum Reserved Bus resource Number.
|
|
@param[in] RsvdPcieMegaMem Reserved Alignment of MEM resource.
|
|
@param[in] PcieMemAddrRngMax Alignment of MEM resource.
|
|
@param[in] RsvdPciePMegaMem Reserved Pcie Kilo Io Number.
|
|
@param[in] PciePMemAddrRngMax Alignment of PMEM resource.
|
|
@param[in] RsvdPcieKiloIo Reserved Pcie Kilo Io Number.
|
|
|
|
**/
|
|
VOID
|
|
HandleResourcePaddingForRootPort (
|
|
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
|
|
IN UINT64 HpcPciAddress,
|
|
OUT UINT8 *RsvdExtraBusNum,
|
|
OUT UINT16 *RsvdPcieMegaMem,
|
|
OUT UINT8 *PcieMemAddrRngMax,
|
|
OUT UINT16 *RsvdPciePMegaMem,
|
|
OUT UINT8 *PciePMemAddrRngMax,
|
|
OUT UINT8 *RsvdPcieKiloIo
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
EFI_STATUS Status2;
|
|
EFI_STATUS Status3;
|
|
EFI_STATUS StatusITbt;
|
|
SA_SETUP SaSetup;
|
|
PCH_SETUP PchSetup;
|
|
SETUP_DATA SetupData;
|
|
UINTN VariableSize;
|
|
UINTN RpIndex = 0;
|
|
UINTN RpBus;
|
|
UINTN RpDev;
|
|
UINTN RpFunc;
|
|
UINT8 PcieRpType = INVALID_RP_CONTROLLER_TYPE;
|
|
UINT8 TbtController;
|
|
ITBT_POLICY_PROTOCOL *ITbtPolicy;
|
|
DXE_ITBT_CONFIG *DxeITbtConfig;
|
|
#if FixedPcdGetBool (PcdDTbtEnable) == 1
|
|
DXE_DTBT_POLICY_PROTOCOL *DxeDTbtConfig;
|
|
Status = gBS->LocateProtocol (
|
|
&gDxeDTbtPolicyProtocolGuid,
|
|
NULL,
|
|
(VOID **) &DxeDTbtConfig
|
|
);
|
|
#endif
|
|
|
|
StatusITbt = gBS->LocateProtocol (&gITbtPolicyProtocolGuid, NULL, (VOID **) &ITbtPolicy);
|
|
if (StatusITbt == EFI_SUCCESS) {
|
|
StatusITbt = GetConfigBlock ((VOID *) ITbtPolicy, &gDxeITbtConfigGuid, (VOID *) &DxeITbtConfig);
|
|
}
|
|
|
|
//
|
|
// Check if PCIe Root HPC Controller need to reserve bus for docking downstream P2P hotplug
|
|
//
|
|
VariableSize = sizeof(SETUP_DATA);
|
|
Status = gRT->GetVariable(
|
|
L"Setup",
|
|
&gSetupVariableGuid,
|
|
NULL,
|
|
&VariableSize,
|
|
&SetupData
|
|
);
|
|
|
|
VariableSize = sizeof(SA_SETUP);
|
|
Status2 = gRT->GetVariable(
|
|
L"SaSetup",
|
|
&gSaSetupVariableGuid,
|
|
NULL,
|
|
&VariableSize,
|
|
&SaSetup
|
|
);
|
|
|
|
VariableSize = sizeof (PCH_SETUP);
|
|
Status3 = gRT->GetVariable (
|
|
L"PchSetup",
|
|
&gPchSetupVariableGuid,
|
|
NULL,
|
|
&VariableSize,
|
|
&PchSetup
|
|
);
|
|
|
|
RpBus = (UINTN) ((HpcPciAddress >> 24) & 0xFF);
|
|
RpDev = (UINTN) ((HpcPciAddress >> 16) & 0xFF);
|
|
RpFunc = (UINTN) ((HpcPciAddress >> 8) & 0xFF);
|
|
|
|
// Get the actual Rootport no corresponding to the device/function no provided
|
|
if ((RpBus == 0) && ((RpDev == SA_PEG_DEV_NUM) || (RpDev == SA_PEG3_DEV_NUM))) {
|
|
// CPU PCIE
|
|
PcieRpType = PCIE_RP_TYPE_CPU;
|
|
RpIndex = RpFunc;
|
|
DEBUG ((DEBUG_INFO, "GetResourcePadding : CPU PCIE Rootport no %02d Bus 0x%x, Device 0x%x, Function 0x%x \n", RpIndex, RpBus, RpDev, RpFunc));
|
|
if (!EFI_ERROR(Status2)) {
|
|
// CPU PCIE
|
|
*RsvdExtraBusNum = SaSetup.PegExtraBusRsvd[RpIndex];
|
|
*RsvdPcieMegaMem = SaSetup.PegMemRsvd[RpIndex];
|
|
*RsvdPcieKiloIo = SaSetup.PegIoRsvd[RpIndex];
|
|
} else {
|
|
Status = EFI_SUCCESS;
|
|
}
|
|
} else if ((RpBus == 0) && ((RpDev == PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1) || (RpDev == PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9) || (RpDev == PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17) || (RpDev == PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25))){
|
|
// PCH PCIE
|
|
PcieRpType = PCIE_RP_TYPE_PCH;
|
|
Status = GetPchPcieRpNumber (RpDev, RpFunc, &RpIndex);
|
|
DEBUG ((DEBUG_INFO, "GetResourcePadding : PCH PCIE Rootport no %02d Bus 0x%x, Device 0x%x, Function 0x%x \n", RpIndex, RpBus, RpDev, RpFunc));
|
|
if (!EFI_ERROR (Status3)) {
|
|
// PCH PCIE
|
|
*RsvdExtraBusNum = PchSetup.PcieExtraBusRsvd[RpIndex];
|
|
*RsvdPcieMegaMem = PchSetup.PcieMemRsvd[RpIndex];
|
|
*RsvdPcieKiloIo = PchSetup.PcieIoRsvd[RpIndex];
|
|
}
|
|
} else if ((RpDev == GetITbtPcieDevNumber ()) && (StatusITbt == EFI_SUCCESS)) {
|
|
GetItbtPciePortIndex (gItbtSegment, RpBus, RpDev, RpFunc, &RpIndex);
|
|
PcieRpType = ITBT_CONTROLLER;
|
|
DEBUG ((DEBUG_INFO, "GetResourcePadding : ITBT Rootport no %02d Bus 0x%x, Device 0x%x, Function 0x%x \n", RpIndex, RpBus, RpDev, RpFunc));
|
|
Status = EFI_SUCCESS;
|
|
} else {
|
|
// Non-Rootport
|
|
DEBUG ((DEBUG_INFO, "GetResourcePadding : Non-Rootport no %02d Bus 0x%x, Device 0x%x, Function 0x%x \n", RpIndex, RpBus, RpDev, RpFunc));
|
|
// Do not assign any IO Resource for this kind of Invalid RP.
|
|
*RsvdPcieKiloIo = 0;
|
|
return;
|
|
}
|
|
|
|
if (!EFI_ERROR (Status)) {
|
|
TbtController = GetRootporttoSetResourcesforTbt (&SetupData, RpIndex, PcieRpType);
|
|
if ((SetupData.IntegratedTbtSupport == 1) && (PcieRpType == ITBT_CONTROLLER)) {
|
|
if (TbtController < MAX_ITBT_PCIE_PORT) {
|
|
if (DxeITbtConfig == NULL) {
|
|
DEBUG ((DEBUG_ERROR, "DxeITbtConfig is NULL \n"));
|
|
return;
|
|
}
|
|
*RsvdExtraBusNum = DxeITbtConfig->ITbtResourceConfig[TbtController].TbtPcieExtraBusRsvd;
|
|
*RsvdPcieMegaMem = DxeITbtConfig->ITbtResourceConfig[TbtController].TbtPcieMemRsvd;
|
|
*PcieMemAddrRngMax = DxeITbtConfig->ITbtResourceConfig[TbtController].TbtPcieMemAddrRngMax;
|
|
*RsvdPciePMegaMem = DxeITbtConfig->ITbtResourceConfig[TbtController].TbtPciePMemRsvd;
|
|
*PciePMemAddrRngMax = DxeITbtConfig->ITbtResourceConfig[TbtController].TbtPciePMemAddrRngMax;
|
|
*RsvdPcieKiloIo = 0;
|
|
}
|
|
}
|
|
#if FixedPcdGetBool (PcdDTbtEnable) == 1
|
|
if ((SetupData.DiscreteTbtSupport == 1) && ((PcieRpType == PCIE_RP_TYPE_PCH) || (PcieRpType == PCIE_RP_TYPE_CPU))) {
|
|
if (TbtController < MAX_DTBT_CONTROLLER_NUMBER) {
|
|
if (DxeDTbtConfig == NULL) {
|
|
DEBUG ((DEBUG_ERROR, "DxeDTbtConfig is NULL \n"));
|
|
return;
|
|
}
|
|
*RsvdExtraBusNum = DxeDTbtConfig->DTbtResourceConfig[TbtController].TbtPcieExtraBusRsvd;
|
|
*RsvdPcieMegaMem = DxeDTbtConfig->DTbtResourceConfig[TbtController].TbtPcieMemRsvd;
|
|
*PcieMemAddrRngMax = DxeDTbtConfig->DTbtResourceConfig[TbtController].TbtPcieMemAddrRngMax;
|
|
*RsvdPciePMegaMem = DxeDTbtConfig->DTbtResourceConfig[TbtController].TbtPciePMemRsvd;
|
|
*PciePMemAddrRngMax = DxeDTbtConfig->DTbtResourceConfig[TbtController].TbtPciePMemAddrRngMax;
|
|
*RsvdPcieKiloIo = 0;
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
}
|
|
|
|
/**
|
|
Handle the Resource Padding For Non-RootPort
|
|
|
|
@param[in] *HpcDevicePath The Device Path to the HPC that is being initialized.
|
|
@param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
|
|
@param[in] RsvdExtraBusNum Reserved Bus resource Number.
|
|
@param[in] RsvdPcieMegaMem Reserved Alignment of MEM resource.
|
|
@param[in] PcieMemAddrRngMax Alignment of MEM resource.
|
|
@param[in] RsvdPciePMegaMem Reserved Pcie Kilo Io Number.
|
|
@param[in] PciePMemAddrRngMax Alignment of PMEM resource.
|
|
@param[in] RsvdPcieKiloIo Reserved Pcie Kilo Io Number.
|
|
|
|
**/
|
|
VOID
|
|
HandleResourcePaddingForNonRootPort (
|
|
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
|
|
IN UINT64 HpcPciAddress,
|
|
OUT UINT8 *RsvdExtraBusNum,
|
|
OUT UINT16 *RsvdPcieMegaMem,
|
|
OUT UINT8 *PcieMemAddrRngMax,
|
|
OUT UINT16 *RsvdPciePMegaMem,
|
|
OUT UINT8 *PciePMemAddrRngMax,
|
|
OUT UINT8 *RsvdPcieKiloIo
|
|
)
|
|
{
|
|
UINT8 RpSeg;
|
|
UINTN RpBus;
|
|
UINTN RpDev;
|
|
UINTN RpFunc;
|
|
UINT64 ParentPciAddress;
|
|
EFI_STATUS Status;
|
|
UINT8 Index;
|
|
UINT8 ConsumedBusNumber;
|
|
|
|
RpSeg = (UINT8) ((HpcPciAddress >> 32) & 0x01);
|
|
RpBus = (UINTN) ((HpcPciAddress >> 24) & 0xFF);
|
|
RpDev = (UINTN) ((HpcPciAddress >> 16) & 0xFF);
|
|
RpFunc = (UINTN) ((HpcPciAddress >> 8) & 0xFF);
|
|
|
|
// Non-Rootport
|
|
DEBUG ((DEBUG_INFO, "GetResourcePadding : Non-Rootport Seg 0x%x, Bus 0x%x, Device 0x%x, Function 0x%x \n", RpSeg, RpBus, RpDev, RpFunc));
|
|
|
|
*RsvdPcieKiloIo = 0;
|
|
ConsumedBusNumber = 0;
|
|
|
|
ParentPciAddress = GetParentPciAddress (RpSeg, RpBus);
|
|
|
|
GetParentResourceSize (ParentPciAddress, RsvdExtraBusNum, RsvdPcieMegaMem, RsvdPciePMegaMem, RsvdPcieKiloIo);
|
|
DEBUG ((DEBUG_INFO, "Parent's resource as below \n"));
|
|
DEBUG ((DEBUG_INFO, "BusNum = %x \n", *RsvdExtraBusNum));
|
|
DEBUG ((DEBUG_INFO, "PcieMegaMem = %x \n", *RsvdPcieMegaMem));
|
|
DEBUG ((DEBUG_INFO, "PciePMegaMem = %x \n", *RsvdPciePMegaMem));
|
|
DEBUG ((DEBUG_INFO, "PcieKiloIo = %x \n", *RsvdPcieKiloIo));
|
|
|
|
CalculateBusConsumptionBeforeAssign (ParentPciAddress, HpcPciAddress, &ConsumedBusNumber);
|
|
|
|
Index = 0;
|
|
Status = GetCurrentBusP2pbHotPlug(RpSeg, (UINT8)RpBus, &Index);
|
|
if (Status == EFI_SUCCESS) {
|
|
// RsvdExtraBusNum = (Reserved Bus - UpStream Bus - DownStream Bus - Tatal Non-HotPlug Bus) / Total HotPlug P2pb
|
|
if (mNumOfHotPlugBridge[Index].NumOfP2pbHotPlug != 0) {
|
|
*RsvdExtraBusNum = (UINT8) DivU64x32Remainder ((UINT64)(*RsvdExtraBusNum - ConsumedBusNumber - mNumOfHotPlugBridge[Index].NumOfP2pbNonHotPlug), (UINT32)mNumOfHotPlugBridge[Index].NumOfP2pbHotPlug, &mRemainderBus);
|
|
}
|
|
|
|
// If mRemainderBus not equal zero, check this device is the last one or not.
|
|
if (mRemainderBus != 0) {
|
|
DEBUG((DEBUG_INFO, "Remainder Bus = %x in the Seg:%x Bus:%x layer\n", mRemainderBus, RpSeg, RpBus));
|
|
if (IsLastP2pbDevice(HpcPciAddress)) {
|
|
DEBUG((DEBUG_INFO, "This device is the last P2pb in the same layer, so we need to add Remainder Bus\n"));
|
|
*RsvdExtraBusNum = (UINT8)(*RsvdExtraBusNum + mRemainderBus);
|
|
}
|
|
}
|
|
*RsvdPcieMegaMem = (*RsvdPcieMegaMem - mNumOfHotPlugBridge[Index].NumOfP2pbNonHotPlug)/mNumOfHotPlugBridge[Index].NumOfP2pbHotPlug;
|
|
*RsvdPciePMegaMem = (*RsvdPciePMegaMem)/mNumOfHotPlugBridge[Index].NumOfP2pbHotPlug;
|
|
*RsvdPcieKiloIo = (*RsvdPcieKiloIo)/mNumOfHotPlugBridge[Index].NumOfP2pbHotPlug;
|
|
DEBUG ((DEBUG_INFO, "Current resource as below \n"));
|
|
DEBUG ((DEBUG_INFO, "BusNum = %x \n", *RsvdExtraBusNum));
|
|
DEBUG ((DEBUG_INFO, "PcieMegaMem = %x \n", *RsvdPcieMegaMem));
|
|
DEBUG ((DEBUG_INFO, "PciePMegaMem = %x \n", *RsvdPciePMegaMem));
|
|
DEBUG ((DEBUG_INFO, "PcieKiloIo = %x \n", *RsvdPcieKiloIo));
|
|
} else {
|
|
DEBUG ((DEBUG_INFO, "GetCurrentBusP2pbHotPlug Status =%r\n", Status));
|
|
}
|
|
}
|
|
|
|
/**
|
|
Returns the resource padding required by the PCI bus that is controlled by the specified Hot Plug Controller.
|
|
|
|
@param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. initialized.
|
|
@param[in] HpcDevicePath The Device Path to the Hot Plug Controller.
|
|
@param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
|
|
@param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_HPC_STATE is defined in section 3.1.
|
|
@param[out] Padding This is the amount of resource padding required by the PCI bus under the control of the specified Hpc. Since the caller does not know the size of this buffer, this buffer is allocated by the callee and freed by the caller.
|
|
@param[out] Attribute Describes how padding is accounted for.
|
|
|
|
@retval EFI_SUCCESS.
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
GetResourcePadding (
|
|
IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
|
|
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
|
|
IN UINT64 HpcPciAddress,
|
|
OUT EFI_HPC_STATE *HpcState,
|
|
OUT VOID **Padding,
|
|
OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
|
|
)
|
|
{
|
|
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource;
|
|
EFI_STATUS Status;
|
|
UINT8 RsvdExtraBusNum = 0;
|
|
UINT16 RsvdPcieMegaMem = 10;
|
|
UINT8 PcieMemAddrRngMax = 1;
|
|
UINT16 RsvdPciePMegaMem = 10;
|
|
UINT8 PciePMemAddrRngMax = 1;
|
|
UINT8 RsvdPcieKiloIo = 4;
|
|
UINTN RpBus;
|
|
CHAR16 *DevicePathStr;
|
|
UINTN VariableSize;
|
|
SA_SETUP SaSetup;
|
|
|
|
PaddingResource = AllocatePool (PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
|
|
ASSERT (PaddingResource != NULL);
|
|
if (PaddingResource == NULL) {
|
|
return EFI_OUT_OF_RESOURCES;
|
|
}
|
|
|
|
*Padding = (VOID *) PaddingResource;
|
|
|
|
// Record the segment number in Bit[32] of HpcPciAddress.
|
|
DevicePathStr = ConvertDevicePathToText (HpcDevicePath, TRUE, TRUE);
|
|
if (DevicePathStr != NULL) {
|
|
if (StrnCmp (DevicePathStr, PCI_ROOT_0_STRING, StrLen (PCI_ROOT_0_STRING)) == 0) {
|
|
DEBUG ((DEBUG_INFO, "Segment0 \n"));
|
|
HpcPciAddress &= ~BIT32;
|
|
} else if (StrnCmp (DevicePathStr, PCI_ROOT_1_STRING, StrLen (PCI_ROOT_1_STRING)) == 0) {
|
|
DEBUG ((DEBUG_INFO, "Segment1 \n"));
|
|
HpcPciAddress |= BIT32;
|
|
}
|
|
} else {
|
|
return EFI_OUT_OF_RESOURCES;
|
|
}
|
|
|
|
RpBus = (UINTN) ((HpcPciAddress >> 24) & 0xFF);
|
|
|
|
if (RpBus == 0x00) {
|
|
//
|
|
// Handle the GetResourcePadding for RootPort
|
|
//
|
|
HandleResourcePaddingForRootPort (
|
|
HpcDevicePath,
|
|
HpcPciAddress,
|
|
&RsvdExtraBusNum,
|
|
&RsvdPcieMegaMem,
|
|
&PcieMemAddrRngMax,
|
|
&RsvdPciePMegaMem,
|
|
&PciePMemAddrRngMax,
|
|
&RsvdPcieKiloIo
|
|
);
|
|
} else {
|
|
//
|
|
// Handle the GetResourcePadding for Non-RootPort
|
|
//
|
|
HandleResourcePaddingForNonRootPort (
|
|
HpcDevicePath,
|
|
HpcPciAddress,
|
|
&RsvdExtraBusNum,
|
|
&RsvdPcieMegaMem,
|
|
&PcieMemAddrRngMax,
|
|
&RsvdPciePMegaMem,
|
|
&PciePMemAddrRngMax,
|
|
&RsvdPcieKiloIo
|
|
);
|
|
}
|
|
|
|
Status = UpdateP2pbResourceRecord (
|
|
HpcDevicePath,
|
|
HpcPciAddress,
|
|
RsvdExtraBusNum,
|
|
RsvdPcieMegaMem,
|
|
PcieMemAddrRngMax,
|
|
RsvdPciePMegaMem,
|
|
PciePMemAddrRngMax,
|
|
RsvdPcieKiloIo
|
|
);
|
|
if (Status == EFI_SUCCESS) {
|
|
mP2pbResourceRecordCount ++;
|
|
}
|
|
|
|
//
|
|
// Padding for bus
|
|
//
|
|
ZeroMem (PaddingResource, PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
|
|
*Attributes = EfiPaddingPciBus;
|
|
|
|
PaddingResource->Desc = 0x8A;
|
|
PaddingResource->Len = 0x2B;
|
|
PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
|
|
PaddingResource->GenFlag = 0x0;
|
|
PaddingResource->SpecificFlag = 0;
|
|
PaddingResource->AddrRangeMin = 0;
|
|
PaddingResource->AddrRangeMax = 0;
|
|
PaddingResource->AddrLen = RsvdExtraBusNum - 1; // Subordinate Bus Number = Secondary Bus Number + Reserved Bus Number, but Secondary Bus Number already consumed 1 bus number itself.
|
|
|
|
//
|
|
// Padding for non-prefetchable memory
|
|
//
|
|
PaddingResource++;
|
|
PaddingResource->Desc = 0x8A;
|
|
PaddingResource->Len = 0x2B;
|
|
PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
|
|
PaddingResource->GenFlag = 0x0;
|
|
|
|
//
|
|
// Check Enable Above 4GB MMIO or not
|
|
//
|
|
VariableSize = sizeof(SA_SETUP);
|
|
Status = gRT->GetVariable (
|
|
L"SaSetup",
|
|
&gSaSetupVariableGuid,
|
|
NULL,
|
|
&VariableSize,
|
|
&SaSetup
|
|
);
|
|
if (!EFI_ERROR(Status)) {
|
|
if (SaSetup.EnableAbove4GBMmio == 1) {
|
|
PaddingResource->AddrSpaceGranularity = 64;
|
|
} else {
|
|
PaddingResource->AddrSpaceGranularity = 32;
|
|
}
|
|
}
|
|
PaddingResource->SpecificFlag = 0;
|
|
//
|
|
// Pad non-prefetchable
|
|
//
|
|
PaddingResource->AddrRangeMin = 0;
|
|
PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
|
|
PaddingResource->AddrRangeMax = (1 << PcieMemAddrRngMax) - 1;
|
|
|
|
//
|
|
// Padding for prefetchable memory
|
|
//
|
|
PaddingResource++;
|
|
PaddingResource->Desc = 0x8A;
|
|
PaddingResource->Len = 0x2B;
|
|
PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
|
|
PaddingResource->GenFlag = 0x0;
|
|
if (!EFI_ERROR(Status) && (SaSetup.EnableAbove4GBMmio == 1)) {
|
|
PaddingResource->AddrSpaceGranularity = 64;
|
|
} else {
|
|
PaddingResource->AddrSpaceGranularity = 32;
|
|
}
|
|
PaddingResource->SpecificFlag = 06;
|
|
//
|
|
// Padding for prefetchable memory
|
|
//
|
|
PaddingResource->AddrRangeMin = 0;
|
|
PaddingResource->AddrLen = (UINT64) RsvdPciePMegaMem * 0x100000;
|
|
//
|
|
// Pad 16 MB of MEM
|
|
//
|
|
PaddingResource->AddrRangeMax = (1 << PciePMemAddrRngMax) - 1;
|
|
|
|
//
|
|
// Alignment
|
|
//
|
|
// Padding for I/O
|
|
//
|
|
PaddingResource++;
|
|
PaddingResource->Desc = 0x8A;
|
|
PaddingResource->Len = 0x2B;
|
|
PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
|
|
PaddingResource->GenFlag = 0x0;
|
|
PaddingResource->SpecificFlag = 0;
|
|
PaddingResource->AddrRangeMin = 0;
|
|
PaddingResource->AddrLen = RsvdPcieKiloIo * 0x400;
|
|
//
|
|
// Pad 4K of IO
|
|
//
|
|
PaddingResource->AddrRangeMax = 1;
|
|
//
|
|
// Alignment
|
|
//
|
|
// Terminate the entries.
|
|
//
|
|
PaddingResource++;
|
|
((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc = ACPI_END_TAG_DESCRIPTOR;
|
|
((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum = 0x0;
|
|
|
|
*HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED;
|
|
|
|
return EFI_SUCCESS;
|
|
}
|