209 lines
9.1 KiB
Plaintext
209 lines
9.1 KiB
Plaintext
/** @file
|
|
This file contains the HWP SSDT Table ASL code.
|
|
|
|
@copyright
|
|
INTEL CONFIDENTIAL
|
|
Copyright 2012 - 2021 Intel Corporation.
|
|
|
|
The source code contained or described herein and all documents related to the
|
|
source code ("Material") are owned by Intel Corporation or its suppliers or
|
|
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
|
and licensors. The Material may contain trade secrets and proprietary and
|
|
confidential information of Intel Corporation and its suppliers and licensors,
|
|
and is protected by worldwide copyright and trade secret laws and treaty
|
|
provisions. No part of the Material may be used, copied, reproduced, modified,
|
|
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
|
without Intel's prior express written permission.
|
|
|
|
No license under any patent, copyright, trade secret or other intellectual
|
|
property right is granted to or conferred upon you by disclosure or delivery
|
|
of the Materials, either expressly, by implication, inducement, estoppel or
|
|
otherwise. Any license under such intellectual property rights must be
|
|
express and approved by Intel in writing.
|
|
|
|
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
|
this notice or any other notice embedded in Materials by Intel or
|
|
Intel's suppliers or licensors in any way.
|
|
|
|
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
|
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
|
the terms of your license agreement with Intel or your vendor. This file may
|
|
be modified by the user, subject to additional terms of the license agreement.
|
|
|
|
@par Specification Reference:
|
|
**/
|
|
|
|
#include "CpuPowerMgmt.h"
|
|
|
|
DefinitionBlock (
|
|
"Cpu0Hwp.aml",
|
|
"SSDT",
|
|
2,
|
|
"PmRef",
|
|
"Cpu0Hwp",
|
|
0x3000
|
|
)
|
|
{
|
|
|
|
External(\_SB.PR00, DeviceObj)
|
|
External(\TCNT, FieldUnitObj)
|
|
External(\_SB.HWPV, IntObj)
|
|
External(\_SB.PR00.CPC2, PkgObj)
|
|
External(\_SB.CFGD, IntObj)
|
|
External(\_SB.LMPS, IntObj)
|
|
External(\_SB.ITBM, IntObj)
|
|
External(\_SB.OSCP, IntObj)
|
|
External(\_SB.HWPE, IntObj)
|
|
External (CORE)
|
|
External (SFBC)
|
|
External (SFSC)
|
|
External (NMFQ)
|
|
External (INFS)
|
|
External (RFBC)
|
|
External (RFSC)
|
|
External (NMFS)
|
|
|
|
// _CPC (Continuous Performance Control)
|
|
// _CPC is a per-processor ACPI object that declares an interface for OSPM to
|
|
// transition the processor into a performance state based on a continuous range
|
|
// of allowable values. Each CPPC register is described in a Generic Register
|
|
// Descriptor format and maps to an unique PCC shared memory
|
|
// location. For a complete description of _CPC object, refer to ACPI 5.0
|
|
// specification, section 8.4.5.1.
|
|
// Arguments: (0)
|
|
// None
|
|
// Return Value:
|
|
// A Package of elements in the following format
|
|
//
|
|
// Package
|
|
// {
|
|
// NumEntries, // Integer
|
|
// Revision, // Integer
|
|
// HighestPerformance, // Generic Register Descriptor
|
|
// NominalPerformance, // Generic Register Descriptor
|
|
// LowestNonlinearPerformance, // Generic Register Descriptor
|
|
// LowestPerformance, // Generic Register Descriptor
|
|
// GuaranteedPerformanceRegister, // Generic Register Descriptor
|
|
// DesiredPerformanceRegister, // Generic Register Descriptor
|
|
// MinimumPerformanceRegister, // Generic Register Descriptor
|
|
// MaximumPerformanceRegister, // Generic Register Descriptor
|
|
// PerformanceReductionToleranceRegister,// Generic Register Descriptor
|
|
// TimeWindowRegister, // Generic Register Descriptor
|
|
// CounterWraparoundTime, // Generic Register Descriptor
|
|
// NominalCounterRegister, // Generic Register Descriptor
|
|
// DeliveredCounterRegister, // Generic Register Descriptor
|
|
// PerformanceLimitedRegister, // Generic Register Descriptor
|
|
// EnableRegister // Generic Register Descriptor
|
|
// }
|
|
Scope(\_SB.PR00)
|
|
{
|
|
|
|
Name(CPOC, Package()
|
|
{
|
|
23, // Number of entries
|
|
03, // Revision
|
|
//
|
|
// Describe processor capabilities
|
|
//
|
|
255, // HighestPerformance fix ratio in integer for OC (255) or ITBM disable with Turbo Boost Max 3.0 supported
|
|
ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Performance - Maximum Non Turbo Ratio
|
|
ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
|
|
ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
|
|
ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
|
|
ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
|
|
ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
|
|
ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
|
|
ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
|
|
ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window register(Null)
|
|
ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
|
|
ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
|
|
ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
|
|
ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
|
|
ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
|
|
1, // Autonomous selection enable register (Exclusively autonomous)
|
|
ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
|
|
ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
|
|
0, // Reference performance (not supported)
|
|
0, // Lowest Frequency (not supported)
|
|
0 // Nominal Frequency
|
|
})
|
|
|
|
Name(CPC3, Package()
|
|
{
|
|
23, // Number of entries
|
|
03, // Revision
|
|
//
|
|
// Describe processor capabilities
|
|
//
|
|
ResourceTemplate() {Register(FFixedHW, 8, 0, 0x771, 4)}, // HighestPerformance
|
|
ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Performance - Maximum Non Turbo Ratio
|
|
ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
|
|
ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
|
|
ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
|
|
ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
|
|
ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
|
|
ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
|
|
ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
|
|
ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window register(Null)
|
|
ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
|
|
ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
|
|
ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
|
|
ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
|
|
ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
|
|
1, // Autonomous selection enable register (Exclusively autonomous)
|
|
ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
|
|
ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
|
|
0, // Reference performance (not supported)
|
|
0, // Lowest Frequency (not supported)
|
|
0, // Nominal Frequency
|
|
})
|
|
|
|
Method(GCPC,1)
|
|
{
|
|
If (INFS) {
|
|
If (And(ShiftRight (CORE, Arg0), BIT0)) {
|
|
Store (SFBC, Index (CPC3, 3))
|
|
Store (SFBC, Index (CPOC, 3))
|
|
Store (RFBC, Index (CPC3, 20))
|
|
Store (RFBC, Index (CPOC, 20))
|
|
Store (NMFQ, Index (CPC3, 22))
|
|
Store (NMFQ, Index (CPOC, 22))
|
|
} Else {
|
|
Store (SFSC, Index (CPC3, 3))
|
|
Store (SFSC, Index (CPOC, 3))
|
|
Store (RFSC, Index (CPC3, 20))
|
|
Store (RFSC, Index (CPOC, 20))
|
|
Store (NMFS, Index (CPC3, 22))
|
|
Store (NMFS, Index (CPOC, 22))
|
|
}
|
|
}
|
|
|
|
//
|
|
// Must return different table if overclocking is enabled CFGD[24] - Overclocking Fully unlocked
|
|
//
|
|
If(And(\_SB.CFGD, PPM_OC_UNLOCKED)) {
|
|
Return(CPOC) // Return CP0C table if version 2 is enabled with overclocking.
|
|
} Else {
|
|
|
|
|
|
If(LAnd(And(\_SB.CFGD, PPM_TURBO_BOOST_MAX), LEqual(\_SB.ITBM, 0))) {
|
|
//
|
|
// Intel Turbo Boost Max Technology 3.0 is available and when policy is disabled
|
|
// Here the _CPC object will report the highest performance of the slowest core.
|
|
//
|
|
If(LNotEqual(\_SB.LMPS, 0)) {
|
|
Return(CPOC)
|
|
}
|
|
}
|
|
Return(CPC3)
|
|
}
|
|
}
|
|
|
|
Method(_CPC,0)
|
|
{
|
|
Return(GCPC(0))
|
|
}
|
|
}// end Scope(\_SB.PR00)
|
|
|
|
}// end of definition block
|