270 lines
8.4 KiB
Plaintext
270 lines
8.4 KiB
Plaintext
/** @file
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Intel Processor Power Management ACPI Code.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include "CpuPowerMgmt.h"
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DefinitionBlock(
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"CPU0TST.aml",
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"SSDT",
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0x02,
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"PmRef",
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"Cpu0Tst",
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0x3000
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)
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{
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External(\_SB.OSCP, IntObj)
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External(\PF00, IntObj)
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External(\TCNT, FieldUnitObj)
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External(\_SB.CTPC, IntObj)
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External(\_SB.CFGD, FieldUnitObj)
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External(\_SB.PR00, DeviceObj)
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External(\_SB.PR00._PSS, PkgObj)
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External(\_SB.PR00.LPSS, PkgObj)
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External(\_SB.PR00.TPSS, PkgObj)
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External (CM00)
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Scope(\_SB.PR00)
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{
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Method(_TPC,0)
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{
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Return(\_SB.CTPC) // Return max T-state available
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}
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//
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// T-State Control/Status interface
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//
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Method(_PTC, 0)
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{
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//
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// IF OSPM is capable of direct access to MSR
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// Report MSR interface
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// ELSE
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// Report I/O interface
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//
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// PDCx[2] = OSPM is capable of direct access to On
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// Demand throttling MSR
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//
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If(And(\PF00, 0x0004)) {
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Return(Package() {
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
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})
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}
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Return(Package() {
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ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)},
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ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)}
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})
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}
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//
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// _TSS package for fine-grained T-State control.
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// "Power" fields are replaced with real values by the first
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// call of _TSS method.
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//
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Name(TSMF, Package() {
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Package(){100, 1000, 0, 0x00, 0},
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Package(){ 94, 940, 0, 0x1F, 0},
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Package(){ 88, 880, 0, 0x1E, 0},
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Package(){ 82, 820, 0, 0x1D, 0},
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Package(){ 75, 760, 0, 0x1C, 0},
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Package(){ 69, 700, 0, 0x1B, 0},
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Package(){ 63, 640, 0, 0x1A, 0},
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Package(){ 57, 580, 0, 0x19, 0},
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Package(){ 50, 520, 0, 0x18, 0},
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Package(){ 44, 460, 0, 0x17, 0},
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Package(){ 38, 400, 0, 0x16, 0},
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Package(){ 32, 340, 0, 0x15, 0},
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Package(){ 25, 280, 0, 0x14, 0},
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Package(){ 19, 220, 0, 0x13, 0},
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Package(){ 13, 160, 0, 0x12, 0},
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Package(){ 7, 100, 0, 0x11, 0}
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})
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//
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// _TSS package for T-State control (Coarse grained)
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// "Power" fields are replaced with real values by the first
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// call of _TSS method.
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//
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Name(TSMC, Package() {
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Package(){100, 1000, 0, 0x00, 0},
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Package(){ 88, 875, 0, 0x1E, 0},
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Package(){ 75, 750, 0, 0x1C, 0},
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Package(){ 63, 625, 0, 0x1A, 0},
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Package(){ 50, 500, 0, 0x18, 0},
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Package(){ 38, 375, 0, 0x16, 0},
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Package(){ 25, 250, 0, 0x14, 0},
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Package(){ 13, 125, 0, 0x12, 0}
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})
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Name(TSSF, 0) // Flag for TSIF/TSIC/TSMF/TSMC initialization
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Mutex(TSMO, 0) // Mutex object to ensure the _TSS initialization code is only executed once
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Method(_TSS, 0)
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{
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//
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// Update "Power" fields of TSIC or TSIF or TSMC or TSMF with the LFM
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// power data IF _PSS is available
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// Power caluclation:
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// n - Number of T-states available
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// _TSS(x).power = LFM.Power * (n-x)/n
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//
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If (LAnd(LNot(TSSF),CondRefOf(\_SB.PR00._PSS)))
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{
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//
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// Acquire Mutex to make sure the initialization happens only once.
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//
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Acquire (TSMO, 0xFFFF)
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//
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// Only one thread will be able to acquire the mutex at a time, but the other threads which have acquired the mutex previously, will eventually try to execute the TSS initialization code.
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// So, let's check if TSS has already been initialized once again. If its initalized, skip the initialization.
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//
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If (LAnd(LNot(TSSF),CondRefOf(\_SB.PR00._PSS)))
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{
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//
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// \_SB.OSCP[10] = Platform-Wide OS Capable for no limit 16 P-states
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//
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If(And(\_SB.OSCP, 0x0400)) {
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Store (SizeOf(\_SB.PR00.TPSS), Local3) //LFM Index from _PSS
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Decrement(Local3) // Index of LFM entry in _PSS
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Store ( DerefOf(Index(DerefOf(Index(\_SB.PR00.TPSS,Local3)),1)),Local5) //LFM Power from _PSS
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} Else {
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Store (SizeOf(\_SB.PR00.LPSS), Local3) //LFM Index from _PSS
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Decrement(Local3) // Index of LFM entry in _PSS
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Store ( DerefOf(Index(DerefOf(Index(\_SB.PR00.LPSS,Local3)),1)),Local5) //LFM Power from _PSS
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}
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//
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// Copy reference of appropiate TSS package based on Fine grained T-state support
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// We'll update the power in the package directly (via the reference variable Local1)
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//
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// If Fine Grained T-states is enabled
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// TSMF
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// ELSE
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// TSMC
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//
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If(And(CFGD,PPM_TSTATE_FINE_GRAINED))
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{
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Store ( RefOf(TSMF), Local1 )
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Store ( SizeOf(TSMF),Local2 )
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}
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Else
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{
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Store ( RefOf(TSMC), Local1 )
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Store ( SizeOf(TSMC),Local2 )
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}
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Store (0, Local0)
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While(LLess(Local0, Local2))
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{
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Store(Divide(Multiply(Local5, Subtract(Local2, Local0)), Local2),
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Local4) // Power for this entry
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Store(Local4,Index(DerefOf(Index(DerefOf(Local1),Local0)),1))
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Increment(Local0)
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}
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Store(Ones, TSSF) // Set flag to indicate TSS table initialization is complete
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}
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Release (TSMO)
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}
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//
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// If Fine Grained T-states is enabled
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// Report TSMF
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// ELSE
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// Report TSMC
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//
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If(And(CFGD, PPM_TSTATE_FINE_GRAINED))
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{
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Return(TSMF)
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}
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Else
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{
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Return(TSMC)
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}
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}
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//
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// Get _TSD
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// Arg0 = CPU Domain ID
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//
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Method(GTSD, 1)
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{
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//
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// IF !(direct access to MSR)
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// Report SW_ANY as the coordination type
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// ELSE
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// Report SW_ALL as the coordination type
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//
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// PDCx[2] = OSPM is capable of direct access to On
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// Demand throttling MSR
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//
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If (LNot(And(\PF00,4))) {
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Return(Package(){ // SW_ANY
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Package(){
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5, // # entries.
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0, // Revision.
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0, // Domain #.
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0xFD, // Coord Type- SW_ANY
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TCNT // # processors.
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}
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})
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}
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Name(STSD,Package() // SW_ALL
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{
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Package() { 5, // # entries.
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0, // Revision
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0, // Domain #.
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0xFC, // Coord Type- SW_ALL
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1 // # processors.
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}
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})
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Store (Arg0, Index(DerefOf(Index(STSD, 0)),2)) // Domain #
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Return(STSD)
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}
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//
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// T-State Dependency
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//
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Method(_TSD, 0)
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{
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Return(GTSD(0))
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}
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}
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} // End of Definition Block
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