87 lines
2.5 KiB
C
87 lines
2.5 KiB
C
/** @file
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Header file for Cpu Information
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CPU_GEN_INFO_H_
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#define _CPU_GEN_INFO_H_
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#include <CpuRegs.h>
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//
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// Processor Definitions
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//
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#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_DT_HALO 0x00090670
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#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE 0x000906A0
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#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_ATOM 0x000B06E0
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///
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/// Enums for CPU Stepping IDs
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///
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typedef enum {
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///
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/// AlderLake DT Steppings
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///
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EnumAdlA0 = 0,
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EnumAdlB0 = 1,
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EnumAdlC0 = 2,
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EnumAdlD0 = 3,
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///
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/// AlderLake Halo Steppings
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///
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EnumAdlG0 = 4,
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EnumAdlH0 = 5,
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///
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/// AlderLake Mobile Steppings(ULT)
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///
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EnumAdlJ0 = 0,
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EnumAdlK0 = 2,
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EnumAdlL0 = 3,
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///
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/// AlderLake Mobile Steppings(ULX)
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///
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EnumAdlQ0 = 1,
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EnumAdlR0 = 4,
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EnumAdlS0 = 5,
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///
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/// Max Stepping
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///
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EnumCpuSteppingMax = CPUID_FULL_STEPPING
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} CPU_STEPPING;
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#endif
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