121 lines
4.8 KiB
C
121 lines
4.8 KiB
C
/** @file
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Header file for PSMI Config
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PSMI_CONFIG_H_
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#define _PSMI_CONFIG_H_
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#include <Base.h>
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#pragma pack (push,1)
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//
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// PSMI Error codes
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//
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#define PSMI_ALLOCATION_SUCCESS 1
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#define ERROR_OUT_OF_RESOURCES 2
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#define ERROR_CACHE_TYPE 3
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#define ERROR_MTRR_SHORTAGE 4
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#define ERROR_NO_ABOVE_4G_MEMORY 5
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//
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// PSMI Trace Memory cache types
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//
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typedef enum {
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RegionDonotCare = 0,
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RegionWriteBack = 1,
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} PSMI_TRACE_CACHE_TYPE;
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#define PSMI_HANDLER_MEMORY_OFFSET_1000 0x1000
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//
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// PSMI Max Trace/Cache Type
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//
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#define MAX_TRACE_REGION 5
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#define MAX_TRACE_CACHE_TYPE 2
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//
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// PSMI Input Scratchpad Register
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//
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typedef union {
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UINT32 RegValue;
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struct {
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UINT32 PsmiHandler:2; /// 1:0 - PSMI Handler Size
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UINT32 TraceRegion0Size:4; /// 5:2 - Trace Region 0 Size
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UINT32 TraceRegion0CacheType:1; /// 6 - Trace Region 0 Cache Type
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UINT32 TraceRegion0RangeCompatible:1; /// 7 - Trace Region 0 Range Compatibility
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UINT32 TraceRegion1Size:4; /// 11:8 - Trace Region 1 Size
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UINT32 TraceRegion1CacheType:1; /// 12 - Trace Region 1 Cache Type
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UINT32 TraceRegion1RangeCompatible:1; /// 13 - Trace Region 1 Range Compatibility
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UINT32 TraceRegion2Size:4; /// 17:14 - Trace Region 2 Size
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UINT32 TraceRegion2CacheType:1; /// 18 - Trace Region 2 Cache Type
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UINT32 TraceRegion2RangeCompatible:1; /// 19 - Trace Region 2 Range Compatibility
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UINT32 TraceRegion3Size:4; /// 23:20 - Trace Region 3 Size
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UINT32 TraceRegion3CacheType:1; /// 24 - Trace Region 3 Cache Type
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UINT32 TraceRegion3RangeCompatible:1; /// 25 - Trace Region 3 Range Compatibility
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UINT32 TraceRegion4Size:4; /// 29:26 - Trace Region 4 Size
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UINT32 TraceRegion4CacheType:1; /// 30 - Trace Region 4 Cache Type
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UINT32 TraceRegion4RangeCompatible:1; /// 31 - Trace Region 4 Range Compatibility
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} Bits;
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} PSMI_INPUT_SCRPD1_REGISTER;
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//
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// PSMI Output Scratchpad Register
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//
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typedef union {
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UINT32 RegValue;
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struct {
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UINT32 PsmiHandlerResultCode:3; /// 2:0 - Handler Error Code
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UINT32 TraceRegion0ResultCode:3; /// 5:3 - Trace Region 0 Error Code
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UINT32 TraceRegion1ResultCode:3; /// 8:6 - Trace Region 1 Error Code
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UINT32 TraceRegion2ResultCode:3; /// 11:9 - Trace Region 2 Error Code
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UINT32 TraceRegion3ResultCode:3; /// 14:12 - Trace Region 3 Error Code
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UINT32 TraceRegion4ResultCode:3; /// 17:15 - Trace Region 4 Error Code
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UINT32 PsmiHandlerBase:14; /// 31:18 - PSMI Handler Base
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} Bits;
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} PSMI_OUTPUT_SCRPD1_REGISTER;
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//
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// PSMI Handler Space Offset 0x1000 Decode
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//
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typedef struct {
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UINT64 PsmiHandlerBaseAddress; /// PSMI Handler BaseAddress
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UINT64 TraceRegion0BaseAddress; /// Trace Region 0 BaseAddress
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UINT64 TraceRegion1BaseAddress; /// Trace Region 1 BaseAddress
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UINT64 TraceRegion2BaseAddress; /// Trace Region 2 BaseAddress
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UINT64 TraceRegion3BaseAddress; /// Trace Region 3 BaseAddress
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UINT64 TraceRegion4BaseAddress; /// Trace Region 4 BaseAddress
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UINT32 PsmiInputRegValue; /// PSMI Request Data
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} PSMI_HANDLER_SPACE_OFFSET;
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#pragma pack (pop)
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#endif
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