90 lines
3.3 KiB
C
90 lines
3.3 KiB
C
/** @file
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Espi policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _ESPI_CONFIG_H_
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#define _ESPI_CONFIG_H_
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#define PCH_ESPI_CONFIG_REVISION 2
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extern EFI_GUID gEspiConfigGuid;
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#pragma pack (push,1)
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/**
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This structure contains the policies which are related to ESPI.
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<b>Revision 1</b>:
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- Initial revision
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<b>Revision 2</b>:
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- Added LockLinkConfiguration field to config block
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range
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specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI).
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<b>0: FALSE</b>, 1: TRUE
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**/
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UINT32 LgmrEnable : 1;
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/**
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eSPI host and device BME settings.
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When TRUE, then the BME bit enabled in eSPI host and device.
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0: FALSE, <b>1: TRUE </b>
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**/
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UINT32 BmeMasterSlaveEnabled : 1;
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/**
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Host HOST_C10 (Virtual Wire) to device Enable (VWHC10OE)
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<b>0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is ignored)</b>
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1b: Enable HOST_C10 reporting to device via eSPI Virtual Wire (upon receiving a HOST_C10 indication from PMC)
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**/
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UINT32 HostC10ReportEnable : 1;
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/**
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eSPI Link Configuration Lock (SBLCL)
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If set to TRUE then communication through SET_CONFIG/GET_CONFIG
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to eSPI device addresses from range 0x0 - 0x7FF
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<b>1: TRUE</b>, 0: FALSE
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**/
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UINT32 LockLinkConfiguration : 1;
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/**
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Hardware Autonomous Enable (HAE)
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If set to TRUE, then the IP may request a PG whenever it is idle
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**/
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UINT32 EspiPmHAE : 1;
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UINT32 RsvdBits : 27; ///< Reserved bits
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} PCH_ESPI_CONFIG;
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#pragma pack (pop)
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#endif // _ESPI_CONFIG_H_
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