262 lines
11 KiB
C
262 lines
11 KiB
C
/** @file
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HDAUDIO policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _HDAUDIO_CONFIG_H_
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#define _HDAUDIO_CONFIG_H_
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#include <ConfigBlock.h>
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#include <PchLimits.h>
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#define HDAUDIO_PREMEM_CONFIG_REVISION 4
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#define HDAUDIO_CONFIG_REVISION 1
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#define HDAUDIO_DXE_CONFIG_REVISION 2
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extern EFI_GUID gHdAudioPreMemConfigGuid;
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extern EFI_GUID gHdAudioConfigGuid;
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extern EFI_GUID gHdAudioDxeConfigGuid;
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#pragma pack (push,1)
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///
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/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
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///
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#define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
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#define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) (UINT32)((UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16))
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#define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof (VerbTable) - sizeof (HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32)))
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///
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/// Use this macro to create HDAUDIO_VERB_TABLE and populate size automatically
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///
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#define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \
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{ \
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{ Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }, \
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{ __VA_ARGS__ } \
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}
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/**
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Azalia verb table header
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Every verb table should contain this defined header and followed by azalia verb commands.
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**/
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typedef struct {
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UINT16 VendorId; ///< Codec Vendor ID
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UINT16 DeviceId; ///< Codec Device ID
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UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
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UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
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UINT16 DataDwords; ///< Number of data DWORDs following the header.
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} HDA_VERB_TABLE_HEADER;
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#ifdef _MSC_VER
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//
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// Disable "zero-sized array in struct/union" extension warning.
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// Used for neater verb table definitions.
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//
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#pragma warning (push)
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#pragma warning (disable: 4200)
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#endif
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typedef struct {
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HDA_VERB_TABLE_HEADER Header;
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UINT32 Data[];
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} HDAUDIO_VERB_TABLE;
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#ifdef _MSC_VER
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#pragma warning (pop)
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#endif
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typedef struct {
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UINT32 ClkA; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_CLKA_*
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UINT32 ClkB; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_CLKB_*
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UINT32 Data; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_DATA_*
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} HDA_DMIC_PIN_MUX;
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/**
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HD Audio Link Policies
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**/
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typedef struct {
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UINT32 Enable : 1; ///< HDA interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits0 : 31;
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UINT8 SdiEnable[PCH_MAX_HDA_SDI]; ///< HDA SDI signal enable. When enabled related SDI pins will be switched to appropriate native mode: <b>0: Disable</b>; 1: Enable
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UINT8 Reserved[(4 - (PCH_MAX_HDA_SDI % 4)) % 4]; ///< Padding for SDI enable table.
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} HDA_LINK_HDA;
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/**
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HD Audio DMIC Interface Policies
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**/
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typedef struct {
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UINT32 Enable : 1; ///< HDA DMIC interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
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UINT32 DmicClockSelect : 2; ///< DMIC link clock select: <b>0: Both</b>, 1: ClkA, 2: ClkB; default is "Both"
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UINT32 RsvdBits0 : 29;
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HDA_DMIC_PIN_MUX PinMux; ///< Pin mux configuration.
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} HDA_LINK_DMIC;
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/**
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HD Audio SSP Interface Policies
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**/
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typedef struct {
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UINT32 Enable : 1; ///< HDA SSP interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits0 : 31;
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} HDA_LINK_SSP;
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/**
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HD Audio SNDW Interface Policies
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**/
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typedef struct {
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UINT32 Enable : 1; ///< HDA SNDW interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits0 : 31;
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} HDA_LINK_SNDW;
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/**
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This structure contains the policies which are related to HD Audio device (cAVS).
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<b>Revision 1:</b>
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- Inital version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable
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UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake initiated by a codec in Sx (eg by modem codec), <b>0: Disable</b>; 1: Enable
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UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0: 6MHz
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UINT32 RsvdBits0 : 26; ///< Reserved bits 0
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/**
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Number of the verb table entry defined in VerbTablePtr.
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Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
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**/
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UINT8 VerbTableEntryNum;
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UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4
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/**
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Pointer to a verb table array.
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This pointer points to 32bits address, and is only eligible and consumed in post mem phase.
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Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
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The prototype of this is:
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HDAUDIO_VERB_TABLE **VerbTablePtr;
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**/
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UINT32 VerbTablePtr;
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} HDAUDIO_CONFIG;
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/**
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This structure contains the premem policies which are related to HD Audio device (cAVS).
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<b>Revision 1:</b>
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- Inital version.
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<b>Revision 2:</b>
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- Add DmicClockSelect
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<b>Revision 3:</b>
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- Add AudioFpgaSocVer
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<b>Revision 4:</b>
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- Remove AudioFpgaSocVer
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 Enable : 1; ///< Intel HD Audio (Azalia) enablement: 0: Disable, <b>1: Enable</b>
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UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
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UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0: VC0</b>, 1: VC1
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/**
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Universal Audio Architecture compliance for DSP enabled system:
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<b>0: Not-UAA Compliant (Intel SST driver supported only)</b>,
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1: UAA Compliant (HDA Inbox driver or SST driver supported)
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**/
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UINT32 DspUaaCompliance : 1;
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UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz
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UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, <b>3: 8T</b>, 4: 16T
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UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconnection, <b>0: Not disconnected, enumerable</b>; 1: Disconnected SDI, not enumerable
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UINT32 PowerGatingSupported : 1; ///< Power Gating supported: <b>0: Not supported</b>, 1: Supported
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UINT32 RsvdBits : 19; ///< Reserved bits 0
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/**
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Audio Link Mode configuration bitmask.
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Allows to configure enablement of the following interfaces: HDA-Link, DMIC, SSP, SoundWire.
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**/
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HDA_LINK_HDA AudioLinkHda; ///< HDA-Link enablement: 0: Disable; <b>1: Enable</b>.
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/**
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DMIC link enablement: 0: Disable; <b>1: Enable</b>.
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DMIC0 LKF: Muxed with SNDW2/SNDW4.
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**/
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HDA_LINK_DMIC AudioLinkDmic [PCH_MAX_HDA_DMIC_LINK_NUM];
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/**
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I2S/SSP link enablement: <b>0: Disable</b>; 1: Enable.
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SSP0/1 LKF: Muxed with HDA.
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@note Since the I2S/SSP2 pin set contains pads which are also used for CNVi purpose, enabling AudioLinkSsp2
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is exclusive with CNVi is present.
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**/
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HDA_LINK_SSP AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM];
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/**
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SoundWire link enablement: <b>0: Disable</b>; 1: Enable.
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SNDW2 LKF: Muxed with DMIC0/DMIC1.
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SNDW3 LKF: Muxed with DMIC1.
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SNDW4 LKF: Muxed with DMIC0.
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**/
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HDA_LINK_SNDW AudioLinkSndw [PCH_MAX_HDA_SNDW_LINK_NUM];
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UINT16 ResetWaitTimer; ///< <b>(Test)</b> The delay timer after Azalia reset, the value is number of microseconds. Default is <b>600</b>.
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UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4
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UINT32 SubSystemIds; ///< Value for SID and SVID. If its set to 0 then default value is used.
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} HDAUDIO_PREMEM_CONFIG;
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typedef struct {
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UINT32 AutonomousClockStop : 1; ///< SoundWire1 link autonomous clock stop capability: <b>0: Disable</b>; 1: Enable
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UINT32 DataOnActiveIntervalSelect : 2; ///< SoundWire1 link data on active interval select 0: 6 clock periods; <b>1: 7 clock periods</b>; 2: 8 clock periods; 3: 11 clock periods
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UINT32 DataOnDelaySelect : 1; ///< SoundWire1 link data on delay select 0: 2 clock periods; <b>1: 3 clock periods</b>
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UINT32 RsvdBits1 : 28; ///< Reserved bits 1
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} HDAUDIO_SNDW_CONFIG;
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/**
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This structure contains the DXE policies which are related to HD Audio device (cAVS).
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<b>Revision 1:</b>
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- Inital version.
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<b>Revision 2:</b>
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- Add IoControlEnabled
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<b>Revision 3:</b>
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- Remove IoControlEnabled
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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SNDW configuration for exposed via SNDW ACPI tables:
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**/
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HDAUDIO_SNDW_CONFIG SndwConfig[PCH_MAX_HDA_SNDW_LINK_NUM];
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/**
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Bitmask of supported DSP features:
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[BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP
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[BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation
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Default is <b>zero</b>.
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**/
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UINT32 DspFeatureMask;
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} HDAUDIO_DXE_CONFIG;
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#pragma pack (pop)
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#endif // _HDAUDIO_CONFIG_H_
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