87 lines
3.9 KiB
C
87 lines
3.9 KiB
C
/** @file
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Interrupt policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _INTERRUPT_CONFIG_H_
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#define _INTERRUPT_CONFIG_H_
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#define PCH_INTERRUPT_CONFIG_REVISION 1
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extern EFI_GUID gInterruptConfigGuid;
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#pragma pack (push,1)
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//
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// --------------------- Interrupts Config ------------------------------
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//
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typedef enum {
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PchNoInt, ///< No Interrupt Pin
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PchIntA,
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PchIntB,
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PchIntC,
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PchIntD
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} PCH_INT_PIN;
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///
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/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
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///
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typedef struct {
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UINT8 Device; ///< Device number
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UINT8 Function; ///< Device function
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UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
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UINT8 Irq; ///< IRQ to be set for device.
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} PCH_DEVICE_INTERRUPT_CONFIG;
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#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 128 ///< Number of all PCH devices
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#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS
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#define PCH_MAX_ITSS_IPC_REGS 4 ///< Number of IPC registers in ITSS
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#define PCH_MAX_ITSS_IRQ_NUM 120 ///< Maximum number of IRQs
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///
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/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
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///
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
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UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
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PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
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UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>.
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UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is <b>9</b>.
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UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is <b>9</b>.
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UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. <b>0: Disable</b>; 1: Enable.
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} PCH_INTERRUPT_CONFIG;
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#pragma pack (pop)
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#endif // _INTERRUPT_CONFIG_H_
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