96 lines
3.7 KiB
C
96 lines
3.7 KiB
C
/** @file
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DMI policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PCH_DMI_CONFIG_H_
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#define _PCH_DMI_CONFIG_H_
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#define PCH_DMI_CONFIG_REVISION 1
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extern EFI_GUID gPchDmiConfigGuid;
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/*
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<b>Revision 1</b>: - Initial version.
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<b>Revision 2</b>: - Added Policies to support FOM
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*/
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#define PCH_DMI_PREMEM_CONFIG_REVISION 2
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extern EFI_GUID gPchDmiPreMemConfigGuid;
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#pragma pack (push,1)
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#define PCH_DMI_HWEQ_COEFFS_MAX 8
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/**
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Lane specific Dmi Gen3, Gen4 equalization parameters.
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**/
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typedef struct {
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UINT8 Cm; ///< Coefficient C-1
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UINT8 Cp; ///< Coefficient C+1
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UINT8 Rsvd0[2]; ///< Reserved bytes
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} PCH_DMI_EQ_PARAM;
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block
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PCH_DMI_EQ_PARAM DmiHwEqGen3CoeffList[PCH_DMI_HWEQ_COEFFS_MAX];
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UINT8 DmiHweq;
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UINT8 Reserved[3];
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} PCH_DMI_PREMEM_CONFIG;
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/**
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The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
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UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
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UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central Write Buffer feature configurable and enabled by default
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UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
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/**
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When set to TRUE turns on:
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- L1 State Controller Power Gating
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- L1 State PHY Data Lane Power Gating
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- PHY Common Lane Power Gating
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- Hardware Autonomous Enable
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- PMC Request Enable and Sleep Enable
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**/
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UINT32 DmiPowerReduction : 1;
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UINT32 ClockGating : 1; ///< 0: Disable; 1: Enable clock gating.
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UINT32 Rsvdbits : 19; ///< Reserved bits
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} PCH_DMI_CONFIG;
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#pragma pack (pop)
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#endif // _PCH_DMI_CONFIG_H_
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