79 lines
3.3 KiB
C
79 lines
3.3 KiB
C
/** @file
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Smbus policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _SMBUS_CONFIG_H_
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#define _SMBUS_CONFIG_H_
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#define PCH_SMBUS_PREMEM_CONFIG_REVISION 1
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extern EFI_GUID gSmbusPreMemConfigGuid;
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#pragma pack (push,1)
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#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
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///
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/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
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///
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typedef struct {
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/**
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Revision 1: Init version
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**/
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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This member describes whether or not the SMBus controller of PCH should be enabled.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 Enable : 1;
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UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
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UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
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///
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/// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
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/// For security recommendations, SPD write disable bit must be set.
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///
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UINT32 SpdWriteDisable : 1;
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UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
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UINT32 RsvdBits0 : 27; ///< Reserved bits
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UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
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UINT8 Rsvd0; ///< Reserved bytes
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UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
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/**
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Array of addresses reserved for non-ARP-capable SMBus devices.
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**/
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UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
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} PCH_SMBUS_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _SMBUS_CONFIG_H_
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