177 lines
9.0 KiB
C
177 lines
9.0 KiB
C
/** @file
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TCSS PEI policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2016 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _TCSS_PEI_CONFIG_H_
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#define _TCSS_PEI_CONFIG_H_
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#include <ConfigBlock.h>
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#include <UsbConfig.h>
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#include <TcssInfo.h>
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#define TCSS_PEI_CONFIG_REVISION 4
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extern EFI_GUID gTcssPeiConfigGuid;
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#pragma pack (push,1)
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#define MAX_IOM_AUX_BIAS_COUNT 4
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///
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/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
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/// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer.
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/// IOM needs know Pull-Up and Pull-Down pin for Bias control
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///
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typedef struct {
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UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
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UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.
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} IOM_AUX_ORI_PAD_CONFIG;
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///
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/// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
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///
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typedef struct {
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UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual VCCST value)
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UINT32 UsbOverride; ///< IOM to override USB connection.
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UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS
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UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS
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} IOM_INTERFACE_CONFIG;
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///
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/// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
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///
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typedef struct {
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UINT8 PmcPdEnable; ///< PMC PD Solution Enable
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UINT8 Rsvd[3];
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} PMC_INTERFACE_CONFIG;
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///
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/// The SA XDCI INT Pin and IRQ number
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///
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typedef struct {
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UINT8 IntPing; ///< Int Pin Number
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UINT8 Irq; ///< Irq Number
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UINT16 Rsvd;
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} SA_XDCI_IRQ_INT_CONFIG;
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///
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/// The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.
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///
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typedef struct {
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UINT8 AcsEnabled; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
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UINT8 DpcEnabled; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
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UINT8 RpDpcExtensionsEnabled; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
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UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
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UINT8 PtmEnabled; ///< Enables PTM capability
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UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>
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UINT8 SlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
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UINT8 SlotPowerLimitScale; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
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UINT16 SlotPowerLimitValue; ///< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
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UINT8 AdvancedErrorReporting; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
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UINT8 UnsupportedRequestReport; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT8 FatalErrorReport; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT8 NoFatalErrorReport; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT8 CorrectableErrorReport; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT8 SystemErrorOnFatalError; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
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UINT8 SystemErrorOnNonFatalError; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
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UINT8 SystemErrorOnCorrectableError; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
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UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Reporting, Max Snoop Latency.
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UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Reporting, Max Non-Snoop Latency.
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UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Snoop Latency Override Mode.
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UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Snoop Latency Override Multiplier.
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UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Snoop Latency Override Value.
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UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
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UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
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UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Value.
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UINT8 ForceLtrOverride; ///< <b>0: Disable</b>; 1: Enable.
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UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
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} TCSS_PCIE_PORT_POLICY;
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///
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/// TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.
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///
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typedef struct {
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TCSS_PCIE_PORT_POLICY PciePortPolicy[MAX_ITBT_PCIE_PORT];
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} TCSS_PCIE_PEI_POLICY;
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///
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/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
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///
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typedef struct {
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UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation Register
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UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation Register
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} TCSS_IOM_ORI_OVERRIDE;
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///
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/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
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///
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typedef struct {
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IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The IOM_AUX_ORI_BIAS_CTRL port config setting.
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TCSS_IOM_ORI_OVERRIDE IomOverrides;
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IOM_INTERFACE_CONFIG IomInterface; ///< Config settings are BIOS <-> IOM interface.
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PMC_INTERFACE_CONFIG PmcInterface; ///< Config settings for BIOS <-> PMC interface
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UINT8 TcStateLimit; ///< Tcss C-State deep stage
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UINT8 Reserved[3]; ///< Reserved bytes for future use
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} TCSS_IOM_PEI_CONFIG;
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///
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/// The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.
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///
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typedef struct {
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SA_XDCI_IRQ_INT_CONFIG SaXdci; ///< System Agent Xdci Int Pin and Irq setting
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UINT8 EnableTcssCovTypeA[MAX_TCSS_USB3_PORTS]; ///< Enable / Disable Type C Port X Convert to TypeA
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UINT8 MappingPchXhciUsbA[MAX_TCSS_USB3_PORTS]; ///< PCH xhci port number for Type C Port x mapping
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UINT8 IomStayInTCColdSeconds; ///< Set IOM stay in TC cold seconds.
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UINT8 IomBeforeEnteringTCColdSeconds; ///< Set IOM before entering TC cold seconds.
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UINT8 Rsvd[2]; ///< Reserved bytes for future use.
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} TCSS_MISC_PEI_CONFIG;
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///
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/// The TCSS_PEI_CONFIG block describes TCSS settings for SA.
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///
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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TCSS_PCIE_PEI_POLICY PciePolicy; ///< The PCIe Config
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USB_CONFIG UsbConfig; ///< USB config is shared between PCH and SA.
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TCSS_IOM_PEI_CONFIG IomConfig; ///< The Iom Config
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TCSS_MISC_PEI_CONFIG MiscConfig; ///< The MISC Config
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} TCSS_PEI_CONFIG;
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#pragma pack (pop)
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#endif /* _TCSS_PEI_CONFIG_H_ */
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